Dynamic Power Management Technology for Embedded Linux-general Linux technology-Linux programming and kernel information. For details, see the following.
Introduction
How to effectively manage embedded systems, especially the power consumption of mobile terminals, is a very valuable topic. Dynamic Power Management DPM (Management) technology provides an operating system level of Power Management capabilities, including CPU operating frequency and voltage, External Bus clock frequency, provides dynamic clock/power adjustment and management functions for external devices. Policies are developed at the user layer to interact with the kernel to provide management functions, so as to adjust power parameters in real time and meet the requirements of real-time system applications, allows power management parameters to be adjusted frequently and with low latency when idle for a short period of time or when tasks are running at low power requirements, enabling finer and more intelligent power management.
1. Dynamic Power Management Principle
The total power consumption of a CMOS circuit is the sum of active power consumption and static power consumption. Active Power Consumption is generated when the circuit is working or the logic state is switched. If no conversion occurs, the transistor leakage will cause static power consumption:
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Type C is a capacitor, fc is the switching frequency, Vdd is the power supply voltage, IQ is the leakage current. C. Vdd. fc indicates active power consumption, and VddIQ indicates static power consumption. In the design and implementation of operating system-level power supply management, the focus is on active power consumption. There are several ways to manage active power consumption:
① Voltage/clock adjustment. Reduces active and static power consumption by reducing the voltage and clock.
② Select the clock. Stop the circuit clock, that is, set fc to O, and set Pactive to 0. Disconnect unused circuit modules to reduce active power consumption. Many CPUs have "idle" or "STOPPED" commands. Some processors can also turn off non-CPU clock modules, such as high-speed cache and DMA peripherals, by means of door-controlled.
③ Select power supply. Disconnect the power supply of unused modules in the circuit. This method requires consideration of the cost of restoring the module.
Disconnecting the clock and power supply of unused modules can reduce power consumption, but correctly predict the idle time of the hardware module. Because re-enabling the hardware module clock and power will cause a certain delay, incorrect predictions will lead to performance degradation.
From formula (1), we can see that the contribution of voltage reduction to power consumption is 2 power, and the lower clock can also reduce power consumption, but it also reduces performance and prolong the execution time of the same task. Set the energy consumption under the 2.0 V high pressure to E high = P high · T, the energy consumption in 1.0 V low voltage is E low = P low · 2 T (in practice, the frequency is approximately linear dependent voltage), and then the formula (1) is easy to get P high = 8 P low. In general, we can conclude that E is high = 4E low, so we should select the minimum clock frequency to meet the performance requirements within the clock frequency and the operating voltage requirements of various system components, setting the lowest power supply voltage will greatly reduce system power consumption. In the preceding example, the energy required to complete the task can be reduced by 75%.
2 hardware platform support for Dynamic Power Management
Hardware Support is required to reduce the active power consumption of the system by adjusting the voltage and frequency. The SoC system generally has multiple execution units, such as the PM (Power Management) module, the OSC (On-chip crystal oscillator) module, and the PLL (Phase-Locked Loop) module) data Cache and command cache in the module, CPU core, and CPU core. Other modules are collectively referred to as peripheral modules (such as 1, CD controller, UART, and SDRAM Controller ). The high-frequency clock of the CPU is mainly provided by the PLL, and other frequency clock is also provided for the peripheral module and the SoC bus. Generally, the SoC system has some divider and multiplier to control these clocks. The PM module mainly manages the power supply status of the system. Generally, it has its own low-frequency, high-accuracy crystal and vibration to maintain an RTC clock, RTC timer, and interrupt control unit. The interrupt control unit enables the RTC timer and external devices to wake up the suspended SoC system. The following uses a TI0MAPl610 processor widely used in handheld devices as an example.
① Clock module. The OMAPl610 provides a digital phase-controlled lock ring (DPLL) that converts the input of an external frequency or crystal oscillator to a high frequency and provides the OMAP 3.2 core and other chip devices. You can set the DPLL output clock by operating DPLLl_CTL_REG, and set the clock reuse register (MUX) and the clock control register ARM_CKCTL to control the Running frequency of MPU and DSP, MPU, DSP peripheral Clock, LCD refresh Clock, TC_CK Clock (Trafflc Control Clock), etc.
② Power management module. OMAPl610 integrates an ultra-low power control module (ULPD) to control OMAP3.2 clock and to control OMAPl610 In and Out of multiple power management modes. You can operate the ULPD control register ULPD_POWER_CTRL to set the processor voltage and manage the running mode.
