MINI2440 IIC Protocol
IIC protocol is widely used in engineering, in my opinion, the advantage of this agreement lies in its hardware and its simple, clear structure.
First , read the IIC protocol for the S3C2440A chip.
The interpretation of the one protocol is analyzed from the above structure. It's nothing more than a four-part. Start by sending the host first.
Manual 484 page, the host send mode block diagram is shown above. Analytical:
1. Configure the host to send mode 2, send slave address and read Data signal 3, ACK 4, send data
Second, the host read data mode.
Manual 485 page, the host receive mode block diagram shows as above. Analytical:
1. Configure the host to receive mode 2, send address and read Signal 3, ACK 4, read data purge interrupt
Third, the setting and processing of interrupts is another key to the resolution protocol. An analysis of the outage of the IIC protocol is now in progress.
For example, manual 488-page IIC control register. The 5th bit is the enable bit for send and receive interrupts. The 4th bit is the interrupt flag bit. If 1, there is an interrupt wait. Write 0 Clear flag.
The generation and processing of interrupts is explained in detail in the 488-page low-end Comment:
As above, by the 2nd, the interrupt source has 3:1 bytes (8bit) of data sent or received, the host (at this time the 2,440-bit slave) call or slave (2440 host) address to the address sent by the host match; arbitration failure (specific follow-up instructions).
Combined with interrupt and host send, receive block diagram, the agreement has a whole grasp, now the problem is the ACK analysis.
Iv. ACK Analysis
Embedded Linux Introduction to Practice (i)