Ethernet Media interfaces: MII rmii smii gmii

Ethernet Media interfaces: MII rmii smii gmii

All these interfaces come from MII. The MII (medium independent interface) means that the media is copper axis, optical fiber, cable, etc, this is because all of these media processing tasks are completed by the phy or Mac chip.
MII supports operations of 10 m and 100 m. An interface consists of 14 lines. Its support is flexible, but there is a disadvantage that it uses too many signal lines for a port, if a vswitch with eight ports needs 112 lines, port 16 requires 224 lines, and port 32 requires 448 lines. Generally, a vswitch is created based on this interface, it is not realistic, so modern switch production will use other standards simplified from MII, such as rmii, smii, and gmii.
Rmii is a simplified MII interface. In terms of data sending and receiving, it is twice the signal line of the MII interface, so it generally requires a 50 MB bus clock. Rmii is generally used in a multi-port switch. Instead of sending and receiving two clocks for each port, a clock is used for sending and receiving all the data ports, this reduces the number of ports. One rmii port requires seven data lines, which is twice less than MII, so the switch can access multiple data ports. Like MII, rmii supports 10 m and 100 M Bus Interface speeds.
Smii is a media interface proposed by Cisco. It has fewer signal lines than rmii, and s indicates serial. Because it only uses one signal line to transmit data and one signal line to transmit and receive data, in order to meet the requirement of 100, the clock frequency is very high, reaching 125 MB, why is 125 MB used? It is because some control information is transmitted in the data line. Smii only uses four signal lines to transmit 100 signals on one port, which is almost twice as short as rmii. Smii is strongly supported in the industry. Similarly, data transmission and receiving on all ports share the same external M clock.
Gmii is the MII interface of gigabit network, which also has the corresponding rgmii interface, indicating the simplified gmii interface.
MII (Media independent interface)
MII is the media independent interface, which is the Ethernet industry standard defined by the IEEE-802.3. It includes a data interface and a management interface between MAC and PHY (figure 1 ). The data interface includes two independent channels used for the transmitter and receiver respectively. Each channel has its own data, clock, and control signal. The MII data interface requires a total of 16 signals. The management interface is a dual-signal interface: one is the clock signal, and the other is the data signal. Through the management interface, the upper layer can monitor and control the phy. The MII management interface has only two signal lines. The configuration and status data is written/read to/from the PHY via the mdio signal.
The MII standard interface is used to connect Fast Ethernet MAC-block and PHY. "Media Independence" indicates that any type of PHY device can work properly without re-designing or replacing the Mac hardware. Interfaces working at other speeds are equivalent to MII: AuI (10 M Ethernet), gmii (Gigabit Ethernet), and xaui (10-Gigabit Ethernet ).
MII Bus
The MII bus specified in 802.3 is a universal bus used to connect different types of PHY to the same network controller (MAC. The network controller can use the same hardware interface and
Gmii (Gigabit MII)
Gmii uses eight-bit interface data with a 125 MHz clock, so the transmission rate can reach 1000 Mbps. It is also compatible with the MII 10/100 Mbps working mode.
The gmii interface data structure complies with the IEEE Ethernet standard. For the interface definition, see IEEE 802.3-2000.
Transmitter:
◇ Gtxclk -- the clock signal of the guitar TX .. signal (125 MHz)
◇ TXCLK--10/M signal clock
◇ Txd [7 .. 0] -- sent data
◇ Txen-transmitter enabling Signal
◇ Txer -- transmitter error (used to destroy a data packet)
Note: gtxclk signals are provided to PHY at a gigabit rate. txd, txen, and txer signals are synchronized with these clock signals. Otherwise, at a rate of 10/100 M, phy provides the txclk clock signal, and other signals are synchronized with this signal. The operating frequency is 25 MHz (2.5 m Network) or MHz (10 m network ).
Receiver:
◇ Rxclk -- receives the clock signal (extracted from the received data, so it is not associated with gtxclk)
◇ Rxd [7 .. 0] -- receives data
◇ Rxdv -- receive valid data indication
◇ Rxer -- receive Data Error Indication
◇ Col-conflict detection (for half duplex only)
Manage configurations
◇ MDC -- configure the interface clock
◇ Mdio -- configure the interface I/O
Manage the configuration interface to control the features of the phy. This interface has 32 register addresses, each of which is 16 bits. Among them, the first 16 have defined the purpose in "IEEE 802.3, 2000-22.2.4 management functions", and the remaining are designated by each device.
Rmii: reduced media independant Interface
Simplified independent media APIs
It is one of the standard Ethernet interfaces and has less I/O transmission than MII.

Questions about rmii and MII
The rmii port uses two wires to transmit data,
The MII port uses four wires to transmit data,
Gmii uses eight wires to transmit data.
MII/rmii is only an interface. For 10 m wire speed, the MII speed is 2.5 m, and rmii is 5 M. For M wire speed, the MII speed is 25 m, rmii is 50 m.
MII/rmii is used to transmit Ethernet packets. The MII/rmii interface is 4/2bit, in the Ethernet phy, serial and encoding/decoding must be performed to transmit data to twisted pair wires and optical fiber cables. The frame format complies with IEEE 802.3 (10 m)/IEEE 802.3u (100 m) /IEEE 802.1Q (VLAN ).
The format of the Ethernet frame is: prefix + start bit + Destination MAC address + source MAC address + type/Length + Data + padding (optional) + 32 bitcrc
If a VLAN exists, a two-byte VLAN tag is added after the type/length. 12 bits represent the vlan id, and 4 bits represent the data priority!