Exynos 4412 clock configuration, exynos4412

Exynos 4412 clock configuration, exynos4412
/*************************************** **************************************** ** @ Author Maoxiao Hu * @ version V1.0.0 * @ date Jan-2015 ************************ **************************************** * ************ <COPYRIGHT 2015 ISE of shandong university> ***************** **************************************** * *********************/this article will improve and correct some minor errors from time to time, also go to http://www.cnblogs.com/humaoxiao to see the latest version. The general method and sequence of clock initialization. u-boot and common bare metal programs can be used if needed. ---------------------------- Problems solved in this article: 1. The clock configuration sequence of several major modules at a macro level. 2. Clock selection, frequency division, and general configuration sequence for small modules. 3. For small modules, the selection of clock sources recommended in the official manual is incorrect. 4. This article only describes "Recommended configurations" in the manual. "Free gameplay" does not guarantee stability. ---------------------------- Multi-path selector selection principle: 1. Try to keep the default configuration unchanged. 2. Select the source with the highest frontend frequency as much as possible. 3. Special situations required by other manuals. ---------------------------- Symbol: dark color on the left: No jitter multi-path selector. No jitter means that the downstream clock can be stabilized when multiple switches are selected. You must ensure that the upstream clock already exists and is stable during the switchover. Otherwise, the downstream clock status is unknown. Light color on the right: there is a jitter multi-channel selector, which means that after multi-channel switching, it will take a period of unstable time, but there is a corresponding register flag indicating that the downstream clock is stable, this type of indicator Register generally starts with CLK_MUX_STAT. ---------------------------- Global constraints: 1. The clock source without jitters must exist and be stable. 2. When a PLL is set to disabled, its output signal cannot be used. ---------------------------- Crystal oscillator Description: Generally, the usb ip core needs to directly use a high-precision clock, so the XUSBXTI pin on the 24 m crystal oscillator, XXTI pin does not need to be connected. In the manual, because the iROM code is designed based on the 24 m crystal oscillator frequency, there is nothing to say about the 24 m choice. ---------------------------- 1. Reasons for clock source PLL configuration: according to global constraints 2, if the PLL is disabled, its output cannot be used, and then according to global constraints 1, the multi-path selector can only select an external clock! However, it is obviously inappropriate to use a 24 m clock directly as the system clock! 4412 has four PLL: APLL, MPLL, EPLL, and VPLL. 24 m external crystal oscillator is recommended as their clock source. Theoretically, the four PLCs can be in the range of 22 ~ The frequency range is as follows:
/* ------------- */APLL & MPLL: 200 ~ 1400 MHzEPLL: 90 ~ 416 MHzVPLL: 100 ~ 440 MHz /*---------------*/
1.0 set PLL_LOCKTIME reason: Refer to http://bbs.eeworld.com.cn/thread-417491-1-1.html

It takes some time for the PLL frequency to change from small to the specified frequency (although the part of the red frame in the figure won't be the actual waveform of the PLL, you can refer to it). When the PLL frequency is changing, for example, the initial 1000 MHz after the reset is increased to MHz. At this time, the CPU frequency is locked first, because the CPU frequency changes at this time, the CPU status cannot be determined. Therefore, use PLL_LOCKTIME to lock the CPU frequency for a period of time until the frequency output is stable. The maximum lock time of APLL is 2400 us (Table 60-9) in the chip manual. If the external crystal oscillator is 24 MHz, US is converted into tick, so

APLL_LOCK (Address: 0x1004_4000) register that writes 0x960

MPLL_LOCK (Address: 0x1004_0008) registers that write 0x190

EPLL_LOCK (Address: 0x1003_C010) register this write 0xBB8

VPLL_LOCK (Address: 0x1003_C020) registers that write data to 0x190.

1.1 APLL & MPLL multiplier value: Set the P, M, and S values of the corresponding register. The final frequencies of different integrations are different and do not need to be calculated by yourself. The recommended integrations are as follows:

1.2 EPLL multiplier value: Set the P, M, S, and K values of the corresponding registers. The final frequencies of different matching are different and do not need to be calculated by yourself. The recommended EPLL values are as follows: 1.3 set the P, M, S, and K values of the corresponding registers for the VPLL multiplier value. The final frequencies of different configurations are different and do not need to be calculated by yourself. The recommended configurations are as follows: 1.4 wait for the PLL to be stable. If the PLL output is stable, the Bit [29] of PLL_CON0 will change from 0 to 1. Query is implemented by Assembly. Take APLL For example:/* --------------------- */wait_pll_lock: ldr r1, [r0, r2] tst r1, #(1 <29) beq wait_pll_lock mov pc, lr ldr r0, = CMU_BASE/* 0x10030000 */ldr r2, = APLL_CON0_OFFSET/* 0x14100 */bl wait_pll_lock /*-----------------------*/
Ii. initialization sequence of main modules