Exynos 4412 power management chip PMIC configuration and usage, exynospmic

Exynos 4412 power management chip PMIC configuration and usage, exynospmic
/*************************************** **************************************** ** @ Author Maoxiao Hu * @ version V1.0.0 * @ date Feb-2015 ************************** **************************************** * *********** <COPYRIGHT 2015 ISE of shandong university> ******************* **************************************** * *******************/this article will improve and correct some minor errors from time to time, please go to the http://www.cnblogs.com/humaoxiao to see the latest version. Development Board: The 4412 best edition. Uboot: uboot-2014-10. PMIC: When SAMSUNG S5M8767A transplanted the new u-boot version, it found that there was almost no information on how to use the power management chip. Even datasheet was hard to download. Why? I can only understand that this part of knowledge is relatively simple and nobody wants to write it. However, there is no harm in recording the principles and usage as a memo. In addition, we still need to declare in advance that only the configuration methods recommended in the official manual are provided here, and the feasibility and Stability of the Free gameplay are not guaranteed. I. Overview of the concepts of LDC and BUCK: Refer to BUCK VS LDC in Embedded circuits. S5M8767A has 9 BUCK and 28 ldos, which can be regarded as a total of 37 power supply circuits. The 37-way power supply circuit can use a step voltage of 6. 25mV at the lowest. up to 60 voltage stalls can precisely control the output voltage. In addition, S5M8767A also has a hardware RTC that can store clock information when powered by an external battery. Ii. Relationship between PMIC and uboot: uboot initializes hardware by module and has its own code order. This requires PMIC to provide power to specific hardware at specific time points in advance, for uboot Initialization Configuration. Otherwise, the execution of uboot will inevitably fail. For example, PMIC needs to supply the two power supplies before eMMC initialization. In addition, the PMIC initialization time has its default time point in uboot. However, this time point is closely related to the actual circuit of the core board and the baseboard, and needs to be delayed or delayed as needed. In PMIC 2.0, BUCK and LDC are classified into two types: BUCK and LDC, which can be directly output by PMIC power-on. The other is that PMIC does not output voltage upon power-on. You need to use i2c to configure PMIC before you can output BUCK and LVS. 2.1 relationship between PMIC and DDR for 4412, DDR Initialization is carried out in BL2. In this case, if you use assembly to initialize hardware i2c to configure PMIC, it makes no sense to myself, therefore, the power supply of the DDR needs to be connected to the PMIC's default on buck, that is, the PMIC can directly output the voltage BUCK after power-ON, without code configuration. We recommend that you use BUCK5 as the power supply for DDR in S5M8767A. However, the default output of BUCK5 is 1.2 V, and the standard 1.5 V is required for DDR. What is the problem? Samsung has long considered this issue for us. In order to adapt to different types of DDR, BUCK5 can use the levels of the K9 K10 pins to output four default voltages: Here, the Development Board of xunwei is set as follows: in this way, B5S1: B5S2 = 1:0 means that the BUCK5 outputs a V voltage, Which is exactly consistent with the requirements of DDR. The relationship between the 2.2 pmic and the 4412 main chip provides the PMIC BUCK2 for the ARM core, and the BUCK2 is also ON by default. The default output is 1.1 V. After reading the 4412 spec, it should be noted that under the 1 V voltage, the APLL that provides the clock to the ARM core can only output a maximum of 1000 MHz, that is, if PMIC is not set during power-on, the ARM core can only work at 1000 MHz and cannot use up to 1.4 GHz. 3. PMIC setting method 3.1 communication protocol S5M8767A uses I2C protocol to communicate with 4412. The slave address is divided into two parts: PM (Power Manager) and RTC, that is to say, the register addresses of PM and RTC are separated and can be considered as two separate chips. 3.2 The following example uses BUCK1 as an example to describe how to set registers. Other BUCK and ldos are similar. Read the manual carefully when necessary: BUCK1 has two 8-bit control registers, you can set the low 6 bits of CTRL1 according to the default value. The high two bits need to be explained. 00 and 1x do not need to be explained. 01 means that the switch of BUCK1 is controlled by the PWREN external pin, the PWREN pin is generally connected with the XPWRRGTON pin of 4412. This XPWRRGTON is automatically controlled by the CPU, and the CPU is in sleep state. This pin is low, and the working status is high, that is to say, once the CPU is out of sleep state, PMIC will power on all BUCK & ldos controlled by PWREN. CTRL2 is used to control the output voltage of BUCK2. The step value of 25mV is calculated by yourself and then written. 4. Reference The PMIC technology of the master on: What is PMU ------------------------ reference start -------------------------------- what is PMU (PMIC) PMU (power management unit) is the power management unit, A highly integrated power management solution for portable applications, that is, a traditional Discrete power management chip, such as a low-voltage differential Linear Voltage Regulator) DC/DC converter (DC/DC), but now they are integrated into the Power Management Unit (PMU) of mobile phones, which can achieve higher power conversion efficiency and lower power consumption, and fewer components to adapt to reduced board-level space, with lower costs. PMU is an integrated power management unit for Consumer Electronics (mobile phones, MP4, GPS, PDAs, and so on, it can provide all power supplies with different voltage levels required by the main chip, and provide different cell phone work units with the same voltage, such as processors, RF devices, and camera modules, enable these units to work properly. Power Management, charging control, and switch control circuit are integrated as needed by the main chip. Including adaptive USB-Compatible PWM charger, multi-channel DC converter (BuckDC-DCconverter), multi-channel Linear Voltage Regulator (ldos), Charge Pump, RTC circuit, motor drive circuit, LCD Backlight Drive Circuit, keyboard Backlight Drive Circuit, keyboard controller, voltage/current/temperature, and other multi-channel 12-BitADC, as well as multi-channel configurable GPIO. In addition, protection circuits such as over/under voltage (OVP/UVP), over temperature (OTP), and over current (OCP) are integrated. Advanced PMU allows safe and transparent power distribution between USB and external AC adapters, lithium batteries, and application system loads. Dynamic Power Path Management (DPPM) is shared between system and battery chargingAC AdapterCurrent, and automatically reduces the charging current when the system load increases.Adjust the relationship between the charging current and the system current distribution to maximize the normal operation of the system,When charging through the USB port, if the input voltage falls below the threshold to prevent the USB port from crashing, the input voltage-based Dynamic Power Management (IDPM) reduces the input current. When the adapter cannot provide peak system current, the Power Path architecture also allows the battery to compensate for this type of system current requirement.
LVS is a voltage regulator that uses a low working pressure difference to adjust the output voltage through negative feedback so that it remains unchanged. If the pressure difference is small, use the ldos, with the shutdown function to facilitate power management. Large Pressure Difference or high efficiency with DC-DC. Various voltage sources are provided as required by the system, which are required for voltage adjustment. In addition, these power supplies can also be turned on and off in sync with functions to support Voltage Field switching. PMU is generally customized with the master chip. Because it must work with the CPU power-on sequence. The power-on sequence of some voltages and the interval between them have a sequential relationship and time requirements. This is a good mask. PMU is actually a dedicated power controller with a mask program. 32.768KHZ crystals and M crystals are required. The STANDBY state is 32.768KHZ crystals, and the normal operation is M. Back to the battery PMIC into the STANDBY state, PMU by 32.768KHZ crystal to provide the clock, press the POWER button to trigger the boot, according to the custom boot order will correspond to the DC-DC open, M master clock operation, after the CPU power is normal, the output settings to the CPU, the output reset signal to the CPU, release the reset signal, CPU start. The CPU output PS_HOLD signal puts PMIC in the working state. (When the power is turned off, the CPU pulls PS_HOLD down and PMIC shuts down.) After the CPU runs normally, you can use the I2C interface to control various PMIC modules. For example, when the system changes the frequency, the core voltage must be adjusted to the corresponding voltage at Different Operating frequencies. RTC time settings and ALARM clock. At the same time, PMIC can generate an interrupt signal to the CPU for exception events, and the CPU can then interrupt the processing. The more PMIC power supply, the smaller the power supply to the system module, and the smaller the power supply to each module, the more power consumption. ---------------------- Reference end -------------------------------- reference: [1] SEC_S5M8767A01-6070_Data sheet_ver.0.10.00_preliminary#[ 2] DS_K4B2G1646Q-BC_Rev103.pdf [3] SEC_Exynos 4412 scp #