Linux Kernel clock interrupt mechanism-general Linux technology-Linux programming and kernel information. The following is a detailed description. Abstract: This article mainly analyzes the clock interruption and Kernel Time Representation of Linux 2.4.0 kernel from the perspective of kernel implementation. This article is intended for readers and Linux driver developers who want to understand the Linux I/O subsystem.
Keywords: Linux, clock, Timer
Note: This document is released in the spirit of free software open source code. Anyone can obtain, use, and re-release it for free, but you have no right to restrict others from re-publishing your content. The purpose of this article is to hope that it can be useful to readers, but it does not have any guarantees, or even implicit guarantees suitable for a specific purpose. For more details, see the GNU General Public License (GPL) and the GNU Free Documentation protocol (GFDL ).
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Preface
Time plays an important role in an operating system kernel. It is the "starter" that drives an operating system kernel ". Generally, the kernel requires two types of time:
1. the current time and date are continuously recorded during kernel running, so that the kernel can mark some objects and events with time (timestamp, also known as "timestamp "), or you can use the time syscall for retrieval.
2. Maintain a fixed-cycle timer to remind the kernel or user that a period of time has elapsed.
The time in the PC is provided by three clock hardware, which are based on fixed frequency crystal oscillator to provide clock square wave signal input. The three Clock hardware types are: (1) Real-Time Clock (RTC); (2) Programmable Interval Timer (Programmable Interval Timer, PIT); (3) time Stamp Counter (TSC ).
Clock hardware 7.1
7.1.1 real-time clock RTC
Since ibm pc at, all PCs have included a clock chip called real-time clock (RTC), so that the PC can continue to maintain time after power failure. Apparently, RTC is powered by a battery on the motherboard, rather than by a PC, so when the PC turns off the power, RTC will continue to work. Generally, cmos ram and RTC are integrated into one chip, so RTC is also called "CMOS Timer ". The most common RTC chips are MC146818 (Motorola) and DS12887 (maxim). DS12887 is fully compatible with MC146818 and has certain extensions. This section is mainly based on the standard RTC chip MC146818. For more information, see Datasheet of MC146818.
7.1.1.1 RTC register
The MC146818 RTC chip has a total of 64 registers. Their internal chip address numbers are 0x00 ~ 0x3F (not the I/O port address), these registers can be divided into three groups:
(1) clock and calendar register group: a total of 10 (0x00 ~ 0x09), indicating the specific time and calendar information. In a PC, the values in these registers are stored in BCD format (for example, 23dec = 0x23BCD ).
(2) Status and control register group: there are 4 (0x0A ~ 0x0D), controls how the RTC chip works, and indicates the current status.
(3) CMOS configuration data: Common cmos ram, which has nothing to do with time, so we don't care about it.
The clock and calendar register groups are described as follows:
Address Function
00 Current second for RTC
01 Alarm second
02 Current minute
03 Alarm minute
04 Current hour
05 Alarm hour
06 Current day of week (01 = Sunday)
07 Current date of month
08 Current month
09 Current year (final two digits, eg: 93)
The format of Status Register A (address 0x0A) is as follows:
Where:
(1) bit [7] -- UIP flag (Update in Progress). If it is set to 1, RTC is updating the value in the calendar register group, at this time, the calendar register group is inaccessible (access to them will get a meaningless gradient value ).
(2) bit [] -- the three operators are divider-control bits, which defines the operation frequency of RTC. Possible values are as follows:
Divider bits Time-base frequency Divider Reset Operation Mode
DV2 DV1 DV0
0 0 0 4.194304 MHZ NO YES
0 0 1 1.048576 MHZ NO YES
0 1 0 32.769 KHZ NO YES
1 0/1 any YES NO
The PC usually sets Divider bits to "010 ".
(3) bit [] -- Rate Selection bits for periodic or square wave signal output.
RS bits 4.194304 or 1.048578 MHZ 32.768 KHZ
RS3 RS2 RS1 RS0 periodic interrupt square wave periodic interrupt Square Wave
0 0 0 0 None
0 0 0 1 30.517 μs 32.768 KHZ 3.90625 ms 256 HZ
0 0 1 0 61.035 μs 16.384 KHZ
0 0 1 122.070 μ s 8.192 KHZ
0 1 0 0 244.141 μs 4.096 KHZ
0 1 0 1 488.281 μs 2.048 KHZ
0 1 1 0 976.562 μ s 1.024 KHZ
0 1 1 1.953125 ms 512 HZ
1 0 0 3.90625 ms 256 HZ
1 0 0 1 7.8125 ms 128 HZ
1 0 1 0 15.625 ms 64 HZ
1 0 1 1 31.25 ms 32 HZ
1 1 0 62.5 ms 16 HZ
1 1 0 1 125 ms 8 HZ
1, 1, 0, 250 ms, 4 HZ
1 1 1 500 ms 2 HZ
The default value of pc bios is "0110 ".
The format of Status Register B is as follows:
The meanings are as follows:
(1) bit [7] -- SET flag. 1 indicates that all update processes of RTC will be terminated, and the user program will immediately initialize the values in the calendar register group. 0 indicates that the update process is allowed to continue.
(2) bit [6] -- PIE mark, indicating periodic interruption enabling.
(3) bit [5] -- AIE flag, indicating the alarm interruption enable.
(4) bit [4] -- UIE mark, indicating the update end interruption enable mark.
(5) bit [3] -- SQWE sign, a square wave signal enabling sign.
(6) bit [2] -- DM flag, used to control the data mode of the calendar register group, 0 = BCD, 1 = BINARY. BIOS always sets it to 0.
(7) bit [1] -- 24/12 mark, used to control the hour register. 0 indicates 12-hour, and 1 indicates 24-hour. Pc bios always sets it to 1.
(8) bit [0] -- DSE flag. BIOS always sets it to 0.
The format of Status Register C is as follows:
(1) bit [7] -- IRQF flag, interrupt request flag. When this bit is 1, it indicates that register B interrupts the request.
(2) bit [6] -- PF mark, periodic interrupt mark. 1 indicates a periodic interrupt request.
(3) bit [5] -- AF flag, alarm interrupt flag. 1 indicates an alarm interrupt request.
(4) bit [4] -- UF flag. The update end interrupt flag is 1, indicating the update end interrupt request.
The format of Status Register D is as follows:
(1) bit [7] -- VRT mark (Valid RAM and Time), 1 indicates OK, 0 indicates RTC has been powered down.
(2) bit [] -- always 0, undefined.
7.1.1.2 access RTC through the I/O port
In a PC, you can read and write registers in the RTC chip through I/O Ports 0x70 and 0x71. Specifically, port 0x70 is the register address index port of RTC, and port 0x71 is the data port.
To read the RTC chip register, follow these steps:
Mov al, addr
Out 70 h, al; Select reg_addr in RTC chip
Jmp $ + 2; a slight delay to settle thing
In al, 71 h;
The steps for writing the RTC register are as follows:
Mov al, addr
Out 70 h, al; Select reg_addr in RTC chip
Jmp $ + 2; a slight delay to settle thing
Mov al, value
Out 71 h, al
7.1.2 programmable interval timer PIT
Each pc has a PIT to generate a periodic clock interruption signal through IRQ0. Currently, the most common Intel 8254 PIT chip is used. Its I/O port address is 0x40 ~ 0x43.
Intel 8254 PIT has three timing channels, each of which has different purposes:
(1) channel 0 is used to update the system clock. Every time a clock is ticking, it generates a clock interruption to the system through IRQ0.
(2) Channel 1 is usually used to control DMAC's RAM refresh.
(3) Channel 2 is connected to a PC speaker to generate a square wave signal.
Each channel has a downward decreasing counter. The frequency of the 8254 PIT input clock signal is 1193181 HZ, that is, 1193181 clock-cycle is entered in one second. Every time you enter a clock-cycle, the counter of the time channel is reduced by 1 and always to 0. Therefore, for Channel 0, when its counter is reduced to 0, PIT generates a clock interruption to the system, indicating that a clock tick has passed. When the counters of each channel are reduced to 0, we say that the channel is in the "Terminal count" state.
The maximum value of the channel counter is 10000 h, and the corresponding clock Interruption Frequency is 1193181/(65536) = 18.2 HZ. That is to say, 18.2 clock interruptions will occur within one second.
7.1.2.1 pit I/O port
On the i386 platform, the I/O port addresses of each register of the 8254 chip are as follows:
Port Description
40 h Channel 0 counter (read/write)
41 h Channel 1 counter (read/write)
42 h Channel 2 counter (read/write)
43 h PIT control word (write only)
Among them, because the counters of channels 0, 1, and 2 are a 16-bit register, the corresponding ports are all 8-bit, therefore, the read/write channel counter must perform two I/O port read/write operations, which correspond to the high bytes and low bytes of the counter respectively, so that the first read/write high bytes and then read and write low bytes, it is determined by the PIT control register. 8254 the PIT control register format is as follows:
(1) bit [] -- Select Counter, Select to operate on that Counter. "00" indicates Counter 0, "01" indicates Counter 1, "10" indicates Counter 2, and "11" indicates Read-Back Command (only for 8254, 8253 is invalid ).
(2) bit [5: 4] -- Read/Write/Latch format bit. "00" indicates the value of the current counter of Latch; "01" indicates the high byte (MSB) of the read-only write counter; "10" indicates the low byte (LSB) of the read-only write counter ); "11" indicates that the LSB of the counter is read and written before MSB.
(3) bit [] -- Mode bits, which controls the operating modes of each channel. "000" corresponds to Mode 0; "001" corresponds to Mode 1; "010" corresponds to Mode 2; "011" corresponds to Mode 3; "100" corresponds to Mode 4; "101" corresponds to Mode 5.
(4) bit [0] -- controls the storage mode of the counter. 0 indicates that the values are stored in binary format, and 1 indicates that the values in the counter are stored in BCD format.
7.1.2.2 working mode of PIT channel
PIT channels can work in the following six modes:
1. Mode 0: an interruption signal is generated when the channel is in the "Terminal count" status.
2. Mode 1: Hardware retriggerable one-shot.
3. Mode 2: Rate Generator. This mode is typically used to generate real-time clock interruptions. At this time, the signal output pin of the channel is set to a high level at the beginning, and continues until the value of the counter is reduced to 1. Then, during the next clock-cycle period, the OUT pin changes to a low level until the counter value is reduced to 0. After the counter value is automatically reloaded, The OUT pin becomes high and repeats the above process. Channel 0 usually works in this mode.
4. Mode 3: Square Wave Signal Generator.
5. Mode 4: Software triggered strobe.
6. Mode 5: Hardware triggered strobe.
7.1.2.3 Latch Counter)
When bit [] in the control register is set to 0, the counter value of the current channel is locked. At this time, you can read a stable counter value through the I/O port, because the counter has stopped counting downward (the PIT chip has not stopped counting downward ). NOTE! Once the lock command is issued, the value of the counter should be read immediately.
7.1.3 timestamp calculator TSC
Starting from Pentium, all Intel 80x86 CPUs contain a 64-bit timestamp register (TSC. This register is actually an ever-increasing counter. It adds 1 to every clock signal of the CPU (that is, when every clock-cycle inputs the CPU, the value of this counter is added to 1 ).
The Assembly command rdtsc can be used to read the value of TSC. With the cpu tsc, the operating system can usually obtain more accurate time measurements. If the frequency of clock-cycle is 400 MHZ, TSC will increase every 2.5 nanoseconds.
Chapter 7 Linux kernel clock interruption
(By Zhan Rongkai, NUDT)
Abstract: This article mainly analyzes the clock interruption and Kernel Time Representation of Linux 2.4.0 kernel from the perspective of kernel implementation. This article is intended for readers and Linux driver developers who want to understand the Linux I/O subsystem.
Keywords: Linux, clock, Timer
Note: This document is released in the spirit of free software open source code. Anyone can obtain, use, and re-release it for free, but you have no right to restrict others from re-publishing your content. The purpose of this article is to hope that it can be useful to readers, but it does not have any guarantees, or even implicit guarantees suitable for a specific purpose. For more details, see the GNU General Public License (GPL) and the GNU Free Documentation protocol (GFDL ).
You should have received a copy of the GNU General Public License (GPL) together with the document. If not, write:
The Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA02139, USA
You are welcome to point out the errors and questions in this document.
Preface
Time plays an important role in an operating system kernel. It is the "starter" that drives an operating system kernel ". Generally, the kernel requires two types of time:
1. the current time and date are continuously recorded during kernel running, so that the kernel can mark some objects and events with time (timestamp, also known as "timestamp "), or you can use the time syscall for retrieval.
2. Maintain a fixed-cycle timer to remind the kernel or user that a period of time has elapsed.
The time in the PC is provided by three clock hardware, which are based on fixed frequency crystal oscillator to provide clock square wave signal input. The three Clock hardware types are: (1) Real-Time Clock (RTC); (2) Programmable Interval Timer (Programmable Interval Timer, PIT); (3) time Stamp Counter (TSC ).
Clock hardware 7.1
7.1.1 real-time clock RTC
Since ibm pc at, all PCs have included a clock chip called real-time clock (RTC), so that the PC can continue to maintain time after power failure. Apparently, RTC is powered by a battery on the motherboard, rather than by a PC, so when the PC turns off the power, RTC will continue to work. Generally, cmos ram and RTC are integrated into one chip, so RTC is also called "CMOS Timer ". The most common RTC chips are MC146818 (Motorola) and DS12887 (maxim). DS12887 is fully compatible with MC146818 and has certain extensions. This section is mainly based on the standard RTC chip MC146818. For more information, see Datasheet of MC146818.
7.1.1.1 RTC register
The MC146818 RTC chip has a total of 64 registers. Their internal chip address numbers are 0x00 ~ 0x3F (not the I/O port address), these registers can be divided into three groups:
(1) clock and calendar register group: a total of 10 (0x00 ~ 0x09), indicating the specific time and calendar information. In a PC, the values in these registers are stored in BCD format (for example, 23dec = 0x23BCD ).
(2) Status and control register group: there are 4 (0x0A ~ 0x0D), controls how the RTC chip works, and indicates the current status.
(3) CMOS configuration data: Common cmos ram, which has nothing to do with time, so we don't care about it.
The clock and calendar register groups are described as follows:
Address Function
00 Current second for RTC
01 Alarm second
02 Current minute
03 Alarm minute
04 Current hour
05 Alarm hour
06 Current day of week (01 = Sunday)
07 Current date of month
08 Current month
09 Current year (final two digits, eg: 93)
The format of Status Register A (address 0x0A) is as follows:
Where:
(1) bit [7] -- UIP flag (Update in Progress). If it is set to 1, RTC is updating the value in the calendar register group, at this time, the calendar register group is inaccessible (access to them will get a meaningless gradient value ).
(2) bit [] -- the three operators are divider-control bits, which defines the operation frequency of RTC. Possible values are as follows:
Divider bits Time-base frequency Divider Reset Operation Mode
DV2 DV1 DV0
0 0 0 4.194304 MHZ NO YES
0 0 1 1.048576 MHZ NO YES
0 1 0 32.769 KHZ NO YES
1 0/1 any YES NO
The PC usually sets Divider bits to "010 ".
(3) bit [] -- Rate Selection bits for periodic or square wave signal output.
RS bits 4.194304 or 1.048578 MHZ 32.768 KHZ
RS3 RS2 RS1 RS0 periodic interrupt square wave periodic interrupt Square Wave
0 0 0 0 None
0 0 0 1 30.517 μs 32.768 KHZ 3.90625 ms 256 HZ
0 0 1 0 61.035 μs 16.384 KHZ
0 0 1 122.070 μ s 8.192 KHZ
0 1 0 0 244.141 μs 4.096 KHZ
0 1 0 1 488.281 μs 2.048 KHZ
0 1 1 0 976.562 μ s 1.024 KHZ
0 1 1 1.953125 ms 512 HZ
1 0 0 3.90625 ms 256 HZ
1 0 0 1 7.8125 ms 128 HZ
1 0 1 0 15.625 ms 64 HZ
1 0 1 1 31.25 ms 32 HZ
1 1 0 62.5 ms 16 HZ
1 1 0 1 125 ms 8 HZ
1, 1, 0, 250 ms, 4 HZ
1 1 1 500 ms 2 HZ
The default value of pc bios is "0110 ".
The format of Status Register B is as follows:
The meanings are as follows:
(1) bit [7] -- SET flag. 1 indicates that all update processes of RTC will be terminated, and the user program will immediately initialize the values in the calendar register group. 0 indicates that the update process is allowed to continue.
(2) bit [6] -- PIE mark, indicating periodic interruption enabling.
(3) bit [5] -- AIE flag, indicating the alarm interruption enable.
(4) bit [4] -- UIE mark, indicating the update end interruption enable mark.
(5) bit [3] -- SQWE sign, a square wave signal enabling sign.
(6) bit [2] -- DM flag, used to control the data mode of the calendar register group, 0 = BCD, 1 = BINARY. BIOS always sets it to 0.
(7) bit [1] -- 24/12 mark, used to control the hour register. 0 indicates 12-hour, and 1 indicates 24-hour. Pc bios always sets it to 1.
(8) bit [0] -- DSE flag. BIOS always sets it to 0.
The format of Status Register C is as follows:
(1) bit [7] -- IRQF flag, interrupt request flag. When this bit is 1, it indicates that register B interrupts the request.
(2) bit [6] -- PF mark, periodic interrupt mark. 1 indicates a periodic interrupt request.
(3) bit [5] -- AF flag, alarm interrupt flag. 1 indicates an alarm interrupt request.
(4) bit [4] -- UF flag. The update end interrupt flag is 1, indicating the update end interrupt request.
The format of Status Register D is as follows:
(1) bit [7] -- VRT mark (Valid RAM and Time), 1 indicates OK, 0 indicates RTC has been powered down.
(2) bit [] -- always 0, undefined.
7.1.1.2 access RTC through the I/O port
In a PC, you can read and write registers in the RTC chip through I/O Ports 0x70 and 0x71. Specifically, port 0x70 is the register address index port of RTC, and port 0x71 is the data port.
To read the RTC chip register, follow these steps:
Mov al, addr
Out 70 h, al; Select reg_addr in RTC chip
Jmp $ + 2; a slight delay to settle thing
In al, 71 h;
The steps for writing the RTC register are as follows:
Mov al, addr
Out 70 h, al; Select reg_addr in RTC chip
Jmp $ + 2; a slight delay to settle thing
Mov al, value
Out 71 h, al
7.1.2 programmable interval timer PIT
Each pc has a PIT to generate a periodic clock interruption signal through IRQ0. Currently, the most common Intel 8254 PIT chip is used. Its I/O port address is 0x40 ~ 0x43.
Intel 8254 PIT has three timing channels, each of which has different purposes:
(1) channel 0 is used to update the system clock. Every time a clock is ticking, it generates a clock interruption to the system through IRQ0.
(2) Channel 1 is usually used to control DMAC's RAM refresh.
(3) Channel 2 is connected to a PC speaker to generate a square wave signal.
Each channel has a downward decreasing counter. The frequency of the 8254 PIT input clock signal is 1193181 HZ, that is, 1193181 clock-cycle is entered in one second. Every time you enter a clock-cycle, the counter of the time channel is reduced by 1 and always to 0. Therefore, for Channel 0, when its counter is reduced to 0, PIT generates a clock interruption to the system, indicating that a clock tick has passed. When the counters of each channel are reduced to 0, we say that the channel is in the "Terminal count" state.
The maximum value of the channel counter is 10000 h, and the corresponding clock Interruption Frequency is 1193181/(65536) = 18.2 HZ. That is to say, 18.2 clock interruptions will occur within one second.
7.1.2.1 pit I/O port
On the i386 platform, the I/O port addresses of each register of the 8254 chip are as follows:
Port Description
40 h Channel 0 counter (read/write)
41 h Channel 1 counter (read/write)
42 h Channel 2 counter (read/write)
43 h PIT control word (write only)
Among them, because the counters of channels 0, 1, and 2 are a 16-bit register, the corresponding ports are all 8-bit, therefore, the read/write channel counter must perform two I/O port read/write operations, which correspond to the high bytes and low bytes of the counter respectively, so that the first read/write high bytes and then read and write low bytes, it is determined by the PIT control register. 8254 the PIT control register format is as follows:
(1) bit [] -- Select Counter, Select to operate on that Counter. "00" indicates Counter 0, "01" indicates Counter 1, "10" indicates Counter 2, and "11" indicates Read-Back Command (only for 8254, 8253 is invalid ).
(2) bit [5: 4] -- Read/Write/Latch format bit. "00" indicates the value of the current counter of Latch; "01" indicates the high byte (MSB) of the read-only write counter; "10" indicates the low byte (LSB) of the read-only write counter ); "11" indicates that the LSB of the counter is read and written before MSB.
(3) bit [] -- Mode bits, which controls the operating modes of each channel. "000" corresponds to Mode 0; "001" corresponds to Mode 1; "010" corresponds to Mode 2; "011" corresponds to Mode 3; "100" corresponds to Mode 4; "101" corresponds to Mode 5.
(4) bit [0] -- controls the storage mode of the counter. 0 indicates that the values are stored in binary format, and 1 indicates that the values in the counter are stored in BCD format.
7.1.2.2 working mode of PIT channel
PIT channels can work in the following six modes:
1. Mode 0: an interruption signal is generated when the channel is in the "Terminal count" status.
2. Mode 1: Hardware retriggerable one-shot.
3. Mode 2: Rate Generator. This mode is typically used to generate real-time clock interruptions. At this time, the signal output pin of the channel is set to a high level at the beginning, and continues until the value of the counter is reduced to 1. Then, during the next clock-cycle period, the OUT pin changes to a low level until the counter value is reduced to 0. After the counter value is automatically reloaded, The OUT pin becomes high and repeats the above process. Channel 0 usually works in this mode.
4. Mode 3: Square Wave Signal Generator.
5. Mode 4: Software triggered strobe.
6. Mode 5: Hardware triggered strobe.
7.1.2.3 Latch Counter)
When bit [] in the control register is set to 0, the counter value of the current channel is locked. At this time, you can read a stable counter value through the I/O port, because the counter has stopped counting downward (the PIT chip has not stopped counting downward ). NOTE! Once the lock command is issued, the value of the counter should be read immediately.
7.1.3 timestamp calculator TSC
Starting from Pentium, all Intel 80x86 CPUs contain a 64-bit timestamp register (TSC. This register is actually an ever-increasing counter. It adds 1 to every clock signal of the CPU (that is, when every clock-cycle inputs the CPU, the value of this counter is added to 1 ).
The Assembly command rdtsc can be used to read the value of TSC. With the cpu tsc, the operating system can usually obtain more accurate time measurements. If the frequency of clock-cycle is 400 MHZ, TSC will increase every 2.5 nanoseconds.
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