Linux USB System (5)

The EHCI Protocol specifies several data models:

Periodic frame list

Asynchronous list queue head pointer

Isochronous (high-speed) Transfer Descriptor (ITD)

Split transaction isochronous transfer Descriptor (sitd)

Queue element transfer Descriptor (QTd)

Queue head

Periodic frame span traversal node (fstn)

The above data model (or data structure) is the key to EHCI. For specific definitions, you can find the ehci spec (enhanced Host Controller Interface Specification for Universal Serial Bus ). The EHCI controller actually manages and operates these data structures.

The EHCI controller standardizes these data models in the form of protocols. The scheme drives designers to design generic drivers and facilitates non-driver designers to reuse their own driver code. To achieve this, EHCI also needs to make some necessary provisions on the hardware part, which is the hardware-to-Software Interface-register.

<> The sequence and function of registers are defined in detail in the following three parts:

PCI configuration registers (USB)

Host Controller capability registers

Host Controller operational registers

We don't have to worry too much about the definition of PCI configuration registers. Generally, arm does not have this part. What we need to know in detail is host controller capability registers and host controller operational registers,

Enhanced host controller capability registers

Offset	Size	Mnemonic	Power well	Register name
00 h	1	Caplength		Capability Register Length
01 H	1	Reserved		N/
02 h	2	Hciversion		Interface version number
04 H	4	Hcsparams		Structural Parameters
08 h	4	Hccparams		Capability Parameters
0ch	8	HCSP-PORTROUTE		Companion port route description

Host Controller operational registers

Offset	Mnemonic	Register name	Power well
00 h	Usbcmd	USB command
04 H	USB STS	USB status
08 h	Usbintr	USB interrupt enable
0ch	Frindex	USB frame Index
10 h	Ctrldssegment	4G segment Selector
14 h	Periodiclistbase	Frame list base address
18 h	Asynclistaddr	Next asynchronous list address
1c-3f	Reserved
40 h	Configflag	Configured flag register
44 h	Portsc (1-n_ports)	Port Status/Control

In some spec of the main chip, the USB master controller is very simple. Most of them just talk about the standard of the USB master controller like me, And then list the register sequence, then let the reader find such a document.

We need to pay attention to the registers marked in red in the above table. The echi master controller uses this as the entry to schedule various data models.

The scheduling of the master controller is mainly divided into two large numbers, one can be called a time slice scheduling. Most controllers mainly use this scheduling method, and the other is asynchronous (asynchronous) scheduling.

In the USB protocol, the USB transmission type is divided into control transmission, batch transmission, interrupted transmission, and other time transmission. The definitions of these transmission types are actually logical. We know that the physical data channel of USB is just one (D +/D-). How can we meet the requirements of these transmission types in the USB protocol, this depends on how the master controller is scheduled.

In EHCI, synchronous transmission and interrupted transmission are controlled by inter-chip scheduling. See:

The so-called time-based scheduling refers to dividing the time per second into several slices (generally 1024/256), and each time slice (FRAME) processes a group of (generally ISO data) data.

The CPU will create a table for ISO data and INT data in the kernel, while the frindex of the echi register will track this table. Each time slice adds-, frindex points out, the controller sends the data in the data structure pointed to by the pointer to the bus. The entire process looks like CPU scheduling.

With the scheduling of time slice, the controller can actually complete all the functions. However, to make it easier for users to use, the Controller also introduces another scheduling method to process data with less real-time requirements.

This kind of debugging is generally called asynchronous scheduling, that is, when asynclistaddr powers up, the CPU arranges block transmission and control transmitted data in the memory according to the protocol-required data structure and creates a linked list, asynclistaddr tracks the linked list, and the Controller moves the data pointed to by asynclistaddr to the USB bus.

Asynchronous scheduling is much easier than ISO scheduling. As for how to coordinate asynchronous debugging and synchronization scheduling, the EHCI controller will solve this problem and no longer need to worry about software.

With the introduction of the above chapter, we know that the EHCI specification has detailed rules on registers, data structures, and control methods. How does Linux implement this rule.

 

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