Makefile explanation,

Makefile explanation,

For your own learning and use only

I. Introduction to Makefile

Makefile or makefile: tells make what to do to maintain a large program. Makefile describes the relationship between modules of the program and the actions required to update modules. make automatically maintains these modules according to these instructions.

When executing the make command, you need a Makefile file to tell the make command how to compile and link the program. Makefile is a database file in the form of text, which contains rules to tell make which files to process and how to process these files. These rules mainly describe which files (called target files) are generated from which other files (called dependency files) are generated, and what command is used to execute this process.

Ii. What does Makefile contain?

Makefile consists of five parts: explicit rules, implicit rules, variable definitions, file instructions, and comments.

1. explicit rules. Explicit rules show how to generate one or more target files. This is clearly pointed out by Makefile writers that the files to be generated, the dependent files of the files, and the generated commands.

2. Concealed rules. Since make has the function of automatic derivation, implicit rules allow us to write Makefile roughly, which is supported by make.

3. variable definition. In Makefile, we need to define a series of variables, which are generally strings. This is a bit of a macro in your c language. When Makefile is executed, all the variables will be extended to the corresponding reference location.

4. File instructions. It consists of three parts: one is to reference another Makefile in a Makefile, just like the include in C; the other is to specify the valid part of The Makefile according to some situations, just like pre-compiled # if in C.

5. comment. Like a UNIX Shell script, Makefile only contains line comments. The comments use the "#" character, which is like "/" or "/*" in C/C ++.

The command in Makefile must start with the [Tab] key !!!

 

The default Makefile file name is GNUmakefile, makefile, or Makefile. Most Linux programmers use the third type. When the make command is executed, the files on the disk are checked. If the generation or change of the target file is at least earlier than one of its dependent files, make will execute the corresponding command to update the target file. The target file is not necessarily the final executable file. It can be any intermediate file and can be used as the dependent file of other target files.

 

 

Reference other makefiles

Makefile uses the include keyword to include other makefiles, which is similar to the # include in C language. The contained files are stored in the original mode of the current file.

The include syntax is:

Include <filename>

Filename can be the file mode of the current operating system Shell (including paths and wildcards)

Make supports three wildcards: "*" and "?". , "[…]"

Include foo. make *. mk $ (bar) is equivalent to: include foo. make a. mk B. mk c. mk e. mk f. mk

Iii. Makefile rules

The Makefile file mainly contains a series of rules, each of which contains the following content:

A target is the final file to be created by make, such as the executable file and the target file. The target can also be the action to be executed, such as "clean ".

One or more dependent files (dependency) List, usually other files required for compiling the target file.

A series of daily commands are the actions executed by make. They usually compile a specified file into a compilation command for the target file. Each command occupies one line, the START character of each command line must be a TAB character.

For example, there are the following Makefile files:

# A simple Makefile example

# Comments starting #

Test: prog. o code. o

Gcc-o test prog. o code. o

Prog. o: prog. c prog. h code. h

Gcc-c prog. c-o prog. o

Code. o: code. c code. h

Gcc-c code. c-o code. o

Clean:

Rm-f *. o

The Makefile above defines four goals: test, prog. o, code. o, and clean. The target is written from the leftmost of each row, followed by a colon (:). If there are other targets or files dependent on the target, column them behind the colon, and separated by spaces. Then start writing a group of commands to achieve this goal in another line. In Makefile, you can use the continuous line number (\) to extend a separate command line into several lines. However, you must note that it cannot be followed by any characters (including spaces and keys) after the continued line number ).

Generally, you can run the following command to call the make command:

# Make target

Target is one of the targets defined in Makefile. If target is omitted, make generates the first target defined in Makefile. For the Makefile example above, a separate "make" command is equivalent:

# Make test

Because test is the first target defined in the Makefile file, all make reads it first and then runs it from the first line, the update of the first target test after the final target affects the update of test. The first rule indicates that as long as the file test timestamp is earlier than any old one in the file prog. o or code. o, the next line of compilation commands will be executed.

However, when checking the file prog. o and code. before the timestamp of o, make will search for. o and code. o is the target rule, and the prog is found in the third row. o rules, the file dependency file is prog. c. prog. h and code. h. Similarly, make will continue to search for the rules of these dependent files in the subsequent rule lines. If the rules cannot be found, it will start to check the timestamps of these dependent files, if any of these files has a timestamp than prog. o, make will execute "gcc-c prog. c-o prog. o "command to update prog. o file.

In the same way, perform a similar check on the file code. o. The dependent files are code. c and code. h. After make executes all these embedded rules, make processes the top-level test rules. For more information about prog. o and code. o. either of the two rules is executed, at least one of them. o the target file will be newer than test, so the command in the test rule should be executed, so make will execute the gcc command to prog. o and code. o connect to the target file test. In the Makefile example above, a target clean is also defined, which is a specialized target commonly used in Makefile, that is, deleting all target modules.

Now let's take a look at the work done by make:

First, make reads the rules in makefile in sequence, and then checks the updated timestamp of the dependent file and the target file in the rule. If the timestamp of the target file is earlier than that of the dependent file, update the target file according to the commands defined in the rule. If the dependency file in the rule is another target file in other rules, follow the rule chain to execute this process until the end of the Makefile file, at least one final dependency file generated by the rule is found, obtain the timestamp of this file, and then execute the old rules of the target file timestamp from bottom to top according to the rule chain until the top-level rule.

Iv. Variables in Makefile

The variables in Makefile are like environment variables. In fact, environment variables are also interpreted as make variables in make. These variables are case sensitive and generally use uppercase letters. Variables can be referenced almost anywhere. The main functions of variables are as follows:

Save the file name list. In the previous example, some target file names of dependent files appear in the executable file rules, and the command line of this rule also contains these files and passes them to gcc as command parameters. If you use a variable to save all target file names, you can easily add new target files without errors.

Save the executable command name, such as the compiler. There are many similar compiler systems in different Linux systems. These systems have slight differences in some places. If a project is used in a non-gcc system, you must change the names of all compilers to the new ones, such as the different compiler versions, such as arm-linux 3.4.1 and 4.3.2. If you use a variable instead of the compiler name, you only need to change the value of the variable. The command names in all other places are changed.

Save the compiler parameters. In many source code compilation scenarios, gcc requires a long set of Parameter options. In many cases, all compilation commands use the same set of options. If you use a variable to represent this set of options, you can place this variable in all places that reference the compiler. To change the option, you only need to change the content of the variable once.

5. Define Variables

Variables in Makefile are defined in Makefile using a text string, which is the value of the variable. You only need to write down the variable name at the beginning of a row, followed by a "=" sign, and set the value of this variable to define the variable. The syntax for defining the variable is as follows:

VARNAME = string

When using the variable, enclose it in parentheses and add the $ symbol before it. The variable value can be referenced: $ {VARNAME}

When the make clause interprets the rule, VARNAME is expanded on the right side of the equation to define its string. Variables are generally defined in the Makefile header. By convention, all Makefile variables should be in uppercase. If the value of the variable changes, you only need to modify it in one place to simplify the maintenance of Makefile.

　　

Now we can use the variables to rewrite the previous Makefile:

OBJS = prog. o code. o

CC = gcc

Test: $ {OBJS}

$ {CC}-o test $ {OBJS}

Prog. o: prog. c prog. h code. h

$ {CC}-c prog. c-o prog. o

Code. o: code. c code. h

$ {CC}-c code. c-o code. o

Clean: rm-f *. o

For example, the source program is

 

 

Makefile file after variable replacement:

6. implicit rules of Makefile

In the above example, the commands used to generate the target file are compiled from the c language source file and related files of ". c" to generate the ". o" target file, which is also a general step. In fact, make can make work more automated. That is to say, make knows some default actions and has some built-in rules called implicit rules, these rules tell make how to execute some commands when the user does not give them completely.

For example, if you delete the commands that generate prog. o and code. o from the rules, make will find the implicit rules and then find and execute an appropriate command. Since these commands use some variables, you can change these variables to customize make. As defined in the previous example, make uses the variable CC to define the compiler, and passes the variable CFLAGS (compiler parameter), CPPFLAGS (C language Preprocessor parameter), TARGET_ARCH (the structure definition of the target machine) to the compiler, and then add the parameter-c, followed by the variable $ <(the first dependent file name ), then the parameter-o plus variable $ @ (target file name ). To sum up, a specific C compilation command will be:

$ {CC }$ {CFLAGS }$ {CPPFLAGS }$ {TARGET_ARCH}-c $ <-o $ @

 

In the preceding example, implicit rules can be simplified:

OBJS = prog. o code. o

CC = gcc

Test: $ {OBJS}

$ {CC}-o $ @ $ ^

Prog. o: prog. c prog. h code. h

Code. o: code. c code. h

Clean: rm-f *. o