Make and Makefile under Linux

Make is used to parse the makefile file

Options for Make:

- D display debug information

The- f file defaults to read dependency information from Makefile or makefile, with this option to change the file

- h Display Help information for all makefile

- N Displays the order in which the makefile executes the command, but does not perform

- S runtime does not display any information

Makefile Format:

Target: Dependency list

<Tab> Command List

The target usually refers to the name of the file to be generated, the executable file or the obj file, or an action name that executes, such as clean

。 Dependency is the material used to produce a target, such as a source file, and a target often has multiple dependencies

A command is an action that executes when a target is generated, and a rule can contain several commands, one for each row

When you do clean, its commands are enforced because clean is not dependent

Clean in make clean is a virtual target that is typically used to delete the files created by make

Makefile Syntax:

# Notes

\ connector, no spaces before and after

?, * wildcard characters

Example 1. HELLO.C File Contents:

#include <stdio.h>int main (void) {printf ("Hello linux!\n"); return 0;}

The contents of the makefile file on hello.c are:

Hello:hello.ogcc-o Hello hello.o or gcc hello.o-o hellohello.o:hello.cgcc-c-o hello.o hello.c or gcc-c hello.c-o hello.o Clean:rm-f *.O

Makefile when multiple files are written:

Example 2. If the source files A.C and B.C can generate the executable file test. The contents of its makefile file are:

TEST:A.O b.o gcc-o test a.o b.o or gcc a.o b.o-o testa.o:a.c gcc-c-o a.o a.c or gcc-c a.c-o A.OB.O:B.C Gcc-c-o b.o b.c or gcc-c b.c-o b.oclean:rm-f *.o

Make executes subsequent commands only when the dependency is newer than the target. You can modify a file time by using the Touch command.

Variables in makefile are defined in the following way: variable: = value

Makefile adds a value to the variable: the variable + = value

The variables in makefile are referenced in the following way: $ (variable name) or ${variable name}, single character variable

For example:

c=gcc

$C

cc=gcc

$ (CC) or ${CC}

Example 3:

In this way, the makefile file for example 1 is modified as:

CC: = gcc Objects: = test.osources: = test.ctest:$ (Objects) $ (cc)-O test $ (Objects) $ (Objects): $ (Sources) $ (CC)-C- o $ (Objects) $ (Sources) clean:rm-f *.O

You can also add the following command to package makefile:

Tar

TAR-CVF Pack.tar Makefile *.c *.h

Execute make tar to package all. C. h and Makefile files in the folder.

Built-in variables in makefile:

[Email protected] The name of the current target

$^ All dependencies

$< is more dependent than the current target update. The first one depends on

$? A dependency list that is newer than the current target. Represents all dependent files that have been modified

Using the built-in variables, the makefile file of Example 3 is modified as:

CC: = gcc Objects: = test.osources: = test.ctest:$ (Objects) $ (cc)-o [email protected] $^$ (Objects): $ (Sources) $ (CC) -c-o [email protected] $^clean:rm-f *.O

Note: The contents of the built-in variable reference are not fixed and vary with the context. For example:

Abc:bcd

The target is ABC, which is dependent on BCD. and

Hello:hello.c

Inside the target is Hello, dependent for hello.c

You can also use the Makefile default recognition method,%.c to represent all. c files, and%.o for all. O Files:

Example: rewrite Example 2:

TEST:A.O B.O gcc-o [email protected] $^ or gcc $^-o [email protected]%.o:%.c gcc-c-o [email protected] $^ or gcc-c $^-o [email protected]clean:rm-f *.o

Makefile If you omit the file name, the target is the same as the dependency by default. At this point, you can omit the dependencies and commands.

For example: Simplify the previous example again:

TEST:A.O B.O gcc-o [email protected] $^ or gcc $^-o [email protected]a.o:b.o:clean:rm-f *.o

Above the

A.O:

B.O:

Two lines can be shortened into one line:

%.O:

Virtual target:

There are some goals in makefile, which are non-existent files and do not need to create them, which are called imaginary targets.

Virtual targets allow you to enforce certain events that do not occur in normal rules.

A virtual target always causes the command associated with it to be executed.

List of common virtual targets:

All generate all executables in the project, usually the first build target of makefile

Clean Delete all files generated by make all

Install the executable files and documents generated by the project in the system directory

Uninstall Delete all files installed by make install

For example, the makefile file for an installation package is as follows:

InstallDir: =/usr/local/bin/install:a b cp-f $^ $ (InstallDir) CD $ (InstallDir); chmod 777 $^ rm-f *.o $^UNINSTALL:CD $ (InstallDir); RM a BA:A.O gcc-o a a.oa.o:a.c gcc-c-o a.o a.cclean:rm-f *.o

You can install it by performing a make install.

Sometimes, in order to prevent the makefile in the virtual target and the actual file name, for example: There is an install file in the actual path, if you execute make install, will be an error. To prevent this, you can precede the virtual target with a modifier, as follows:

. Phony:clean

Plus, even if you have a file with the same name, you won't get an error.

The following example executes make all to generate all the targets:

All:test Hello

Test:test.o

.....

hello:hello.o

....

Makefile Common errors:

1. The tab is replaced by a space. Workaround: Cat-t Makefile to view tabs in makefile: ^i

2. A space is inserted between the connector ' \ ' and the line break. Workaround: Cat-e makefile. The newline character is displayed with $.

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Make and Makefile under Linux