milestone/umts_sholes/omap3430 DSS (Display sub-system) Go-through

This is a creation in Article, where the information may have evolved or changed. milestone/umts_sholes/omap3430 DSS (Display sub-system) Go-through

Past life:
Why did you turn over 10 years of milestone, time-consuming and laborious sync the code on GitHub, compiling the Umts_sholes project?
A question about reading and writing an LCD screen through a read-write FB0 device node is now a high-pass solution msm8974/msm8x26 by reading and writing fb0 device nodes
Cannot complete the read/write LCD screen operation.

To fully understand this problem, first of all, we need to know how Tiny6410/milestone reads and writes the LCD screen by reading and writing fb0 device nodes.
The impression of CM7 umts_sholes using 2ndboot boot kernel rom is to write/dev/graphics/fb0 this device node to brush 2ndboot image to the LCD.
Therefore, we studied the OMAP3430 DSS. Needless to say, use the code TRM to illustrate the problem.

/home/corpusers/xxxx/projects/umts_sholes/out/target/product/umts_sholes/system/bin/sh_hijack.sh

#!/system/bin/sh    echo >/sys/devices/platform/omapfb/graphics/fb0/bits_per_pixel    echo 1 >/sys/ Devices/omapdss/display0/update_mode    /system/bin/busybox_static gunzip-c/etc/2ndboot/2ndboot.fb.gz >/dev/ graphics/fb0    /system/bin/busybox_static Insmod/etc/2ndboot/hbootmod.ko >/cache/2ndboot.log 2>&1    /system/bin/busybox_static Mknod/dev/hbootctrl C 245 0 >>/cache/2ndboot.log 2>&1    echo 255 >/S Ys/class/leds/green/brightness    /system/bin/hbootuser/etc/2ndboot/hboot.cfg >>/cache/2ndboot.log 2> &1    /system/bin/busybox_static Sleep 10

With Omap3430-trm.pdf (http://www.droid-developers.org/images/0/0b/Omap3430-trm.pdf), you can see the main module of the OMAP3430 DSS: Display Controller Module (DISPC), display Serial Interface (DSI), Serial display Interface (SDI CONFIG_OMAP2_DSS_SDI
Does not open, so umts_sholes does not use SDI, using DSI).

The Big picture

Milestone the way to brush the LCD through the FB0 device node:
# cat/dev/graphics/fb0 >/MNT/SDCARD/UMTS_SHOLES.FB


Before forcing the LCD to be set to 1, auto update mode, the Update_mode is manual update modes by default.
Manual Update mode requires that the dirty be set to actually write to the LCD.

Enum Omapfb_update_mode {omapfb_update_disabled = 0,omapfb_auto_update,omapfb_manual_update};

static int dsi_update_thread (void *data) {struct Omap_dss_device *device;u16 x, y, W, h;u8 num_timeouts = 0;u8 num_success = 0;while (1) {bool Sched;wait_event_interruptible (Dsi.waitqueue,dsi.update_mode = = Omap_dss_update_auto | | (Dsi.update_mode = = Omap_dss_update_manual && Dsi.update_region.dirty = true) | | Kthread_should_stop ()); if (Kthread_should_stop ()) break;

# echo 1 >/sys/devices/omapdss/display0/update_mode
# CAT/MNT/SDCARD/UMTS_SHOLES.FB >/dev/graphics/fb0

The read-write/dev/graphics/fb0 character device node corresponds to the drive file_operations fb_fops located in Fbmem.c,

static const struct File_operations fb_fops = {. Owner =this_module,.read =fb_read,.write =fb_write,.unlocked_ioctl = fb_i Octl, #ifdef config_compat.compat_ioctl = Fb_compat_ioctl, #endif. mmap =fb_mmap,.open =fb_open,.release =fb_release,# ifdef Have_arch_fb_unmapped_area.get_unmapped_area = Get_fb_unmapped_area, #endif #ifdef CONFIG_FB_DEFERRED_IO.fsync =fb_deferred_io_fsync, #endif};

Static ssize_tfb_write (struct file *file, const char __user *buf, size_t count, loff_t *ppos) {//This function pointer is Null.if (info-> Fbops->fb_write) return Info->fbops->fb_write (info, buf, count, PPOs);//The effective code for writing LCD is this section//info->screen _base Save is framebuffer SDRAM in the virtual address,//this memory address in the DSS driver will be assigned to the DISPC Display Controller of a register,//DISPC is responsible for Sdra This memory data transfer in M is sent via the data cable to LCD.DST = (u32 __iomem *) (info->screen_base + p); while (count) {c = (count > Page_size)? PAGE_SIZE:COUNT;SRC = buffer;if (Copy_from_user (SRC, buf, c)) {err =-efault;break;} for (i = C >> 2; i--;) Fb_writel (*src++, dst++), if (C & 3) {U8 *src8 = (U8 *) src;u8 __iomem *dst8 = (U8 __iomem *) dst;for (i = c & 3; I --; ) Fb_writeb (*src8++, dst8++);d st = (u32 __iomem *) dst8;} *ppos + = c;buf + c;cnt + c;count-= c;}

Omap3430-trm.pdf <display Subsystem Basic Programming model>
The Dss.dispc_gfx_baj registers mentioned in this section is the register to write framebuffer SDRAM Address.

15.5.3.2 Graphics Layer Configuration

15.5.3.2.1 Graphics DMA Registers

15.5.3.3 Video Layer Configuration

15.5.3.3.1 Video DMA Registers

Look at the structure of the driver.
~/projects/umts_sholes/kernel/drivers/video/omap2$ Tree
.
├──displays
│├──kconfig
│├──makefile
│├──omap-panel.c

│├──panel-mapphone.c

├──dss
│├──core.c
│├──dispc.c
│├──display.c
│├──dpi.c
│├──dsi.c
│├──dss.c
│├──dss.h
│├──kconfig
│├──makefile
│├──manager.c
│├──overlay.c
│├──rfbi.c

│└──venc.c
├──kconfig
├──makefile
├──misc
│├──dispsw.c
│├──dispsw-mr.c
│├──dispsw-mr.h
│├──dispsw-rotate.c
│├──dispsw-rotate.h
│├──kconfig
│└──makefile
├──omapfb
│├──kconfig
│├──makefile
│├──omapfb.h
│├──omapfb-ioctl.c
│├──omapfb-main.c
│└──omapfb-sysfs.c
├──vram.c
└──vrfb.c


4 directories, all files

~/projects/umts_sholes/kernel/drivers/video/omap2$ grep-nr "Dispc_gfx".
./dss/dispc.c:75: #define DISPC_GFX_BA0 Dispc_reg (0x0080)
./dss/dispc.c:76: #define DISPC_GFX_BA1 Dispc_reg (0x0084)
./dss/dispc.c:77: #define Dispc_gfx_position Dispc_reg (0x0088)
./dss/dispc.c:78: #define Dispc_gfx_size Dispc_reg (0x008c)
./dss/dispc.c:79: #define Dispc_gfx_attributes Dispc_reg (0X00A0)
./dss/dispc.c:80: #define Dispc_gfx_fifo_threshold Dispc_reg (0X00A4)
./dss/dispc.c:81: #define Dispc_gfx_fifo_size_status Dispc_reg (0X00A8)
./dss/dispc.c:82: #define Dispc_gfx_row_inc Dispc_reg (0X00AC)
./dss/dispc.c:83: #define Dispc_gfx_pixel_inc Dispc_reg (0x00b0)
./dss/dispc.c:84: #define Dispc_gfx_window_skip Dispc_reg (0X00B4)
./dss/dispc.c:85: #define Dispc_gfx_table_ba Dispc_reg (0X00B8)
./dss/dispc.c:95: #define Dispc_gfx_preload Dispc_reg (0x022c)

static void _dispc_set_plane_ba0 (enum Omap_plane plane, u32 paddr) {const struct Dispc_reg ba0_reg[] = {Dispc_gfx_ba0,disp C_VID_BA0 (0), dispc_vid_ba0 (1)};d Ispc_write_reg (Ba0_reg[plane], paddr);//paddr is the corresponding physical address in framebuffer SDRAM}

Invoke process
Dsi_update_thread
Dss_setup_partial_planes
-Configure_dispc (void)
Configure_overlay
_dispc_setup_plane
_DISPC_SET_PLANE_BA0 (plane, paddr + offset0);
_DISPC_SET_PLANE_BA1 (plane, paddr + offset1);

For Sync/build umts_sholes source code, please refer to the following articles:

http://blog.csdn.net/fervor_heart/article/details/10060557

That ' s all! Thanks!