Xilinx announces Launch of SDAccel development environment for OpenCL, C and C + +

Source: Internet
Author: User

Xilinx, Inc. (NASDAQ:XLNX), the world leader in Programmable technology and devices, announced today the launch of OpenCL, C and c+ at the 2014 International Super Computing 2014 + SDACCELTM development environment, increase unit power performance by up to 25 times times, thereby using FPGA to achieve Data Center application acceleration. SDAccel is the newest member of the Xilinx SDX series, combining the industry's first architecture-optimized compilers, libraries, and boards with any combination of OpenCL, C, and C + + cores to achieve a completely similar CPU/GPU development and runtime experience on FPGAs for the first time.

Robert Hormuth, executive director of Dell's platform architecture and Technology and CTO office, said: "FPGA-based technology has a new breakthrough to support optimized computing applications." In the process of Dell server deployment, simplifying programming is a key hurdle in determining the adoption of FPGA accelerators ... There is no doubt that Xilinx opens up the right path for developers to use a software environment to improve the productivity of FPGA platform users. ”

Vice president of IBM Power Development and president of the OpenPOWER Foundation (IBM Vice president of power development and OpenPOWER President) Brad McCredie said: " IBM highly appreciates Xilinx's commitment to the development of its FPGA software programmability.Samsung CasinoCreating optimized FPGA accelerators with high flexibility and reliable result quality with C, C + +, and OpenCL can improve IBM's ability to deliver greater value to its customers. IBM believes that OpenCL is a great boon to productivity, and we are working closely with Xilinx to apply this technology to our OpenPOWER product design. ”

First architecture-optimized compiler for OPENCL, C, and C + +

The SDAccel Architecture Optimizer compiler has a 25 times-fold increase in unit power performance relative to the CPU or GPU, and 3 times times more performance and resource efficiency than other FPGA solutions. SDAccel employs a base compiler technology that has been widely used by more than 1,000 programmers. SDAccel leverages the compiler's capabilities to enable software developers to create high-performance accelerators with new or existing OpenCL, C, and C + + code, and for storage in various data center applications such as computational search, image recognition, machine learning, encoding conversion, storage compression and encryption, Data flow and pipelining technology are carefully optimized.

First implementation of a completely similar CPU/GPU development experience on FPGAs

With SDAccel, developers can use their familiar workflow to optimize their applications and benefit from the advantages of the FPGA platform, even without prior experience with FPGA. The Integrated Design Environment (IDE) not only provides coding templates and software libraries, but also compiles, debugs, and features analysis of a variety of development goals, such as emulation on X86 platforms, performance verification using fast simulations, and local execution on FPGA processors. The IDE performs the application on the FPGA platform in the data center. The platform provides automatic instrument insertion for all supporting development goals. In addition, SDAccel has been carefully designed to enable CPU/GPU developers to easily migrate their applications to FPGAs while maintaining and reusing OpenCL, C, and C + + code in their familiar workflow.

The comprehensive SDAccel environment includes the IDE for programmers, the C-based FPGA optimization library, and the off-the-shelf commercial (COTS) platform for data centers.

The SDAccel library includes built-in OpenCL functions, DSP, video, and linear algebra libraries for high-performance, low-power implementations. For specific areas of acceleration, Xilinx Alliance partner Auviz Systems offers a well-optimized OPENCV and Blas OPENCL-compliant software library. The original COTS membership includes Alpha Data, convey, Pico Computing, and additional members are expected to be added early in 2015.

Full and Cpu/gpu uptime experience for the first time on FPGA

Only SDAccel can support applications with multiple programs and similar CPU/GPU on-demand loadable compute units. Similar to Cpu/gpu, SDAccel's unique approach to FPGA solutions is the ability to keep the system working during the program conversion process. SDAccel is the only environment in the industry that can create an FPGA compute unit that loads new accelerator cores while the application is running. Key system interfaces and functions, such as memory, Ethernet, PCIe, and Performance Monitor, remain operational throughout the execution of the application. Instantly reconfigurable compute units allow multiple applications to share FPGA accelerators. For example, the switching between image search, video transcoding, and image processing can be supported by programming the operating system.

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Xilinx announces Launch of SDAccel development environment for OpenCL, C and C + +

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