How to design the I2C bus EEPROM driver in Linux

I2C (Inter-IntegratedCircuit1 bus is a 2-line serial bus developed by Philips, used to connect

1 Introduction

I2C (Inter-Integrated Circuit1 bus is a two-line serial bus developed by Philips to connect the microcontroller and its peripheral devices. It is a special form of synchronous communication. it has the advantages of few interface lines, simple control mode, small encapsulation form, and high communication rate. In master-slave communication, multiple I2C bus devices can be connected to the I2C bus at the same time and the communication objects can be identified by addresses. During the development of an embedded Linux system based on the MPC8250, the author found that the I2C bus is widely used in embedded systems and there are many types of I2C bus controllers, the operation interfaces provided by the system vary greatly. The slave devices connected to the I2C bus mainly include microcontroller, EEPROM, real-time clock, and A/D converter. the MPC8250 processor uses an internal I2C bus controller to exchange data with these devices connected to the I2C bus. Due to the characteristics of I2C bus, drivers of Linux I2C bus equipment adopt a unique architecture when designing drivers. There is a big difference between developing I2C bus device drivers and developing general device drivers. Therefore, the development of I2C bus device drivers should not only involve the knowledge of general Linux kernel drivers. We also need to have a deep understanding of the I2C bus driver architecture. During the development process, the author uses the EEPROM of the device model AT24C01A to test the I2C bus driver.

2 Working principle overview

Before introducing the I2C bus structure. Two concepts should be clarified: I2C bus controller and I2C device. The I2C bus controller provides an interface for the microcontroller or microprocessor to control the I2C bus. it controls the special sequence, protocol, arbitration, and timing of all I2C buses. This refers to the I2C bus control interface provided by the MPC8250. An I2C device is a device connected to a microcontroller or microprocessor through an I2C bus, such as an EEPROM or LCD driver.

In a serial data channel, the I2C bus controller can be configured in Master mode or slave mode. During the development, the I2C Bus Controller of the MPC8250 works in the master mode and serves as the master device. The I2C device connected to the bus is the AT24C01A type EEPROM and acts as the slave device. Both the master and slave devices can work in the receiving and sending status. The bus must be controlled by the master device. the master device generates a serial clock to control the transmission direction of the bus and generates start and stop conditions.

2.1 I2C Bus Controller

I2C uses a two-line structure consisting of the serial data line SDA and the serial clock line SCL to exchange data between the external IC and the controller. The I2C Bus Controller of the MPC8250 includes the sending and receiving units, an independent baud rate generator, and a control unit. The sending and receiving units use the same clock signal if I2C is the master device. The clock signal is generated by the I2C baud rate generator. if I2C is a slave device, the clock signal is provided externally.

Two-way SDA and SCL are connected to the forward voltage through external + 3.3 V pull-up resistance. When the bus is idle, both SDA and SCL should be high, as shown in the general I2C configuration mode 1.

I2C configuration mode

The receiving and sending units of I2C are both dual-Cache. when data is sent, the data is output from the sending data register to the shift register at the clock rate to the SDA line. when the data is received, the data enters the shift register from the SDA line and then the Receiving Register.

2.2 Basic I2C bus controller and EEPROM operations

The I2C bus has three types of signals during data transmission: start signal, end signal, and response signal.

Start signal: in high-power mode, SDA switches from high level to low level to start transmitting data;

End signal: in high-power mode, SDA changes from low-level to high-level, and data transmission ends;

Response signal: After receiving a byte of data, the device that receives the data sends a specific low-level pulse to the device that sends the data. Indicates that the data has been received.

When the I2C bus of the MPC8250 is idle, the SDA and SCL are both high. the master device starts the sending process by sending a start signal. The timing requirement of this signal is that when the SCL is high, the SDA will have a jump from high to low. After the start condition. It must be from the device address byte, where the 4-bit high is the device type identifier (different chip types have different definitions, the EEPROM should generally be 1010), and the 3-bit is selected as the chip, the last one is the read/write bit. when the value is 1, the read operation is performed. if the value is 0, the write operation is performed, as shown in figure 2.

EEPROM device address byte structure

If the master device needs to write data to the EEPROM, the master device sends a write request (R/W = 0) to the EEPROM in the address byte. the sent address byte is followed by the data to be sent. Each time one byte of data is sent, the EEPROM generates a response signal, and the main device also monitors the response signal. if the EEPROM does not return a response signal after one byte is sent, the master device stops sending and generates an end signal. The write operation sequence is shown in 3.

I2C Master device write operation sequence

To read data from the EEPROM, set R/W = 1. After one byte of data is sent by the EEPROM, the primary device generates a response signal to notify the EEPROM primary device to request more data, each response signal EEPROM generated by the primary device sends one byte of data. This operation ends when the primary device does not send a response signal and then sends an end signal bit. The read operation sequence 4 is shown in.

I2C Master device read operation sequence

3. I2C bus driver architecture in Linux

In Linux, for a given I2C bus hardware configuration system, the I2C bus driver architecture consists of an I2C bus driver and an I2C device driver. The I2C bus driver includes a specific controller driver and an I2C bus algorithm driver. An algorithm driver is applicable to a class of bus controllers. A specific bus controller driver uses a certain algorithm. For example, the algorithm i2e-algo-8260 provided in the Linux kernel can be used on the I2C bus controller provided by the MPC82xx series processor. The Linux kernel provides algorithm drivers for common processors such as the MPC82xx series. For I2C devices, each specific device has its own basic features. Its drivers generally require special design.