How to inline ASM in C (GCC)

How to inline ASM in C (GCC)

I have tested it. This is a helloworld. It prints Hello World on the screen and runs normally:
Code:
# Include <pspkernel. h>
# Include <pspdebug. h>

Psp_module_info ("Hello World", 0, 1, 1 );

Int main (void ){
Char * MSG = "Hello world! /N ";
Pspdebugscreeninit ();
ASM ("lui $4, % Hi (% 0)/n"
"Jal pspdebugscreenprintf/N"
"Addiu $4, $4, % Lo (% 0)/n"
"NOP/N"
: "G" (MSG ));
Return 0;
}

Lui, Load upper immediate.
$4, $4 will be loaded later.
% Hi, This will grab the upper 16 bits of (VAL ).
$0, This is this first argument passed into the function.
Jal, Jump and load.
Pspdebugscreenprintf, The JAL loads pspdebugscreenprintf and that prints $4.

Addiu, Add immmediate unsigned.
$4, $4, % Lo (% 0), $4 + % Lo (% 0)(Lower 16 bits of the first arguement passed into the function) = $4.

NOP, No operation. This means that instead of setting $4 after Jal, you can set before. This is used for aligning code.

: "G" (MSG ));, Loads the variable MSG ($0) and ends the ASM function. This requires-02 on GCC, if that isnt by default.

Write makefile like this
Target = Hello
Objs = Main. o

Cflags =-O2-G0-wall
Cxxflags = $ (cflags)-fno-exceptions-fno-rtti
Asflags = $ (cflags)

Extra_targets = eboot. pbp
Psp_eboot_title = Hello world in ASM

Pspsdk = $ (shell PSP-config -- pspsdk-path)
Include $ (pspsdk)/lib/build. Mak

More detailed instructions

MIPs r4000 microprocessor Instruction List
This information was taken from the MIPs r4000 microprocessor User Manual

Load and store
Load and store instructions move data between memory and General registers. they are all immediate (I-type) Instructions, since the only addressing mode supported is base register plus 16-bit, signed immediate offset.

Load and store instructions

Opcode description
LBLoad byte
LbuLoad byte unsigned
LHLoad halfword
LhuLoad halfword unsigned
LWLoad word
LWLLoad word left
LWRLoad word right
SbStore byte
ShStore halfword
SWStore word
SWLStore word left
SWRStore word right

Computational
Computation instructions perform arithmetic, logical, shift, multiply and divide operation on values in registers. they include register (R-type, in which both the operands and the result are stored in registers) and immediate (I-type, in which one operand
Is a 16-bit immediate value) formats.

Arithmetic instructions (ALU immediate)

Opcode description
AddiAdd immediate
AddiuAdd immmediate unsigned
SltiSet on less than immediate
SltiuSet on less than immediate unsigned
AndIAnd immediate
OriOr immediate
XoriExclusive or immediate
LuiLoad upper immediate

Arithmetic (3-operand, R-type)

Opcode description
AddAdd
AdduAdd unsigned
SubSubtract
SubuSubtract unsigned
SLTSet on less
SlyuSet on less than unsigned
AndAnd
OrOr
XORExclusive or
NorNor

Multiply and divide instructions

Opcode description
MultMultiply
MultuMultiply unsigned
DivDivide
DivuDivide unsigned
MfhiMove from hi
MthiMove to hi
MfloMove from Lo
MtloMove to Lo

Jump and branch
Jump and branch instructions change the control flow of a program. jumps are always made to a paged, absolute address formed by combining a 26-bit target address with the high-order bits of the program counter (J-Type format) or register address (R-Type format ).
Branches have 16-bit offsets relative to the program counter (I-type). Jump and link instructions save their return address in register 31.

Jump and branch instructions

OpcodeDescription
JJump
JalJump and link
JRJump and register
JalrJump and link register
BeqBranch on equal
BNEBranch on not equal
BlezBranch on less than or equal to zero
BgtzBranch on greater than zero
BLTZBranch on Less Than Zero
BgezBranch on greater Thn or equal to zero
BltzalBranch on less than zero and link
BgezalBranch on greater than or equal to zero and link

Shift instructions

Opcode description
SllShift left logical
SRLShift right logical
SRAShit right artithmetic
SllvShift left logical retriable
SrlvShift right logical variable
SravShift right artithmetic variable

Coprocessor
Coprocessor instructions perform operations in the coprocessors. coprocessor load and store instructions are I-type.

Coprocessor 0 (system coprocessor)
Coprocessor 0 (system coprocessor) Instructions perform operations on cp0 registers to control the memory management and exception handling facilities of the processor.

Coprocessor instructions

Opcode description
LwczLoad word to coprocessor Z
SWCZStore word from coprocessor Z
MtczMove to coprocessor Z
MfczMove from coprocessor Z
CtczMove control to coprocessor Z
CfczMove control from coprocessor Z
CopzCoprocessor operation Z
BcztBranch on coprocessor Z true
BczfBranch on coprocessor Z false

Special
Special instructions perform system CILS and breakpoint operations. These instructions are always r-type.

Special instructions

Opcode description
SyscallSystem Call
BreakBreak

 

MIPs Compilation
MIPs ASM tutorial
Http://kedem.cs.duke.edu/cps104/Handouts/MIPS-asm.pdf
MIPs user book
Http://hitmen.c02.at/files/docs/psp/R4400_Uman_book_Ed2.pdf