This time is still on the Cemera. With the interrupt pin EINT20 is also GPG12.
There is an infrared receiver on the 51 board previously welded.
Please note that it is
Standard NEC Code specification:
The first transmission is a high-level pulse of 9ms, followed by a low level of 4.5ms, followed by the 8bit address code (starting from the low-effective bit),
The inverse of the address code of the 8bit (mainly for error checking). Then the 8bit command code (also starting from the low-effective bit),
Then it is the inverse code of the 8bit Command code. Its "0" for the carrier emission 0.56ms, does not emit 0.565ms, its "1" for the carrier transmission 0.56ms,
Do not launch 1.69ms.
This is a less-than-good way to implement, and it will update other better algorithms later.
The principle is relatively simple, when there is interruption, the GPG12 is set as input function, through the reading pin level, with the time, you can get the code issued by the infrared remote control.
Code Total 4, factory ID high, factory ID Low, command, command anti-code
After testing, it was found that the command was normal for only 6 bits lower,
Drive source
1#include <linux/consolemap.h>2#include <linux/module.h>3#include <linux/sched.h>4#include <linux/tty.h>5#include <linux/tty_flip.h>6#include <linux/mm.h>7#include <linux/string.h>8#include <linux/init.h>9#include <linux/slab.h>Ten One#include <linux/kbd_kern.h> A#include <linux/kbd_diacr.h> -#include <linux/vt_kern.h> -#include <linux/input.h> the#include <linux/reboot.h> -#include <linux/notifier.h> -#include <linux/jiffies.h> -#include <linux/uaccess.h> + -#include <asm/irq_regs.h> +#include <linux/interrupt.h> A#include <linux/irq.h> at#include <linux/delay.h> - -#include <linux/gpio.h> -#include <mach/regs-gpio.h> -#include <mach/gpio-samsung.h> -#include <mach/hardware.h> in#include <plat/gpio-cfg.h> - to /* + Standard NEC Code specification: - The first transmission is a high-level pulse of 9ms, followed by a low level of 4.5ms, followed by the 8bit address code (starting from the low-effective bit), the The inverse of the address code of the 8bit (mainly for error checking). Then the 8bit command code (also starting from the low-effective bit), * then it is the inverse code of the 8bit Command code. Its "0" for the carrier emission 0.56ms, does not emit 0.565ms, its "1" for the carrier transmission 0.56ms, $ do not launch 1.69ms. Panax Notoginseng */ - the #defineIR Gpio_get_value (S3C2410_GPG (12)) + A StaticIrqreturn_t IRM_IRQ (intIrqvoid*dev_id) the { + intk,i; -UnsignedCharirm_code[4] = {0,0,0,0}; $ $ /*operating principle when there is an interrupt occurs in the configuration pin function for GPIO input type Direct read IRM signal level high and low*/ -S3c_gpio_cfgpin (S3C2410_GPG ( A), s3c2410_gpio_input); -Mdelay (5);//must be low in 9ms or not header the if(0==IR) - {Wuyi while(! IR);//wait for the high level of 4.5ms the - //detects if it is 2.5ms re WuMdelay (3); - if(1==IR) About { $ //k 4-bit encoding - for(k=0; k<4; k++) - { - //i 8bit for each encoding A for(i=0;i<8; i++) + { the while(IR);//wait turns low - while(! IR);//after the wait has changed to high level $Udelay ( the);//sleep after 700us read value theIrm_code[k] |= (IR &1) <<i;//Save Low First the } the } the - //Calculate the correct code code in if((irm_code[2]&0x3f) = = (~ (irm_code[3]) &0x3f)) the { thePrintk"fid:0x%x 0x%x cid:0x%x 0x%x\n", irm_code[0], irm_code[1], irm_code[2], irm_code[3]); About } the } the } theS3c_gpio_cfgpin (S3C2410_GPG ( A), S3C2410_GPIO_IRQ); + returnirq_handled; - } the Bayi Static intIrm_init (void) the { the intret; - //register interrupt rising Edge trigger -ret = REQUEST_IRQ (irq_eint20, IRM_IRQ, irqf_trigger_rising,"IRM_IRQ", NULL); the return 0; the } the the Static voidIrm_exit (void) - { the Free_irq (irq_eint20, NULL); the } the 94 Module_init (irm_init); the Module_exit (irm_exit); theModule_license ("GPL");
IRM3800 infrared remote control decoding Linux driver