Learn the assembly instructions that the Linux kernel often encounters (1)

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reprint: http://blog.sina.com.cn/s/blog_4be6adec01007xvg.html80X86 Assembly instruction Symbol Daquan
+ 、-、 *,/: arithmetic operator.

&: Macro handling operators. Macro extensions do not recognize the formal parameters in symbols and strings, and if you precede the formal parameter with a & token, the macro assembler can replace the formal parameter with a real parameter.

$: The value of the address counter--records the address of the statement being translated by the assembler. Each segment is assigned a counter, and the offset address of all labels and variables defined within the segment is the value of the current assembly address counter.

?: Operand. In the data definition statement, the operand is used? , its role is to allocate and retain storage space, but not to deposit the determined data.

=: equal sign pseudo-directive--symbol definition. Symbols are defined and assigned, functionally similar to equ, but allowed (duplicated) to be redefined.

:: Modify the attribute operator (operator)--segment operator. Used to temporarily assign a segment attribute to a variable, label, or address expression (without the default segment register), which automatically generates a "cross-segment prefix byte". Note that the segment register CS and ES cannot be spanned, and the stack operation cannot span the SS.

;: Comment symbol.

%: Special macro operator used to convert the subsequent expression (usually a symbolic constant, not a variable name and register name) to the value it represents, and embed the ASCII code of this value into the macro extension.

(): 1. Operator--Used to change the precedence level of the operator. 2. The textbook symbol, which indicates the contents of the storage unit (or register) in parentheses.

<: A macro called to enclose a string (as an argument) with a spacer (such as a space, a comma, and so on).

[]:1. Operator. The number enclosed in square brackets is the subscript or address expression of the array variable. The address expression with square brackets must follow the following principles, ① only BX, BP, SI, di these four registers can appear in square brackets; ②BX or BP can appear in brackets alone, or in square brackets with constants, SI, or DI, but not BX and BP in the same square brackets , ③si and Di can appear alone in the brackets, but also with constants, BP or BX in square brackets, but do not allow Si and di in the same square brackets; ④ contains multiple registers in a square bracket, they can only be used for addition operations; ⑤ if the square brackets contain the base pointer BP, It implicitly uses the stack segment register SS to provide the segment base, otherwise it implicitly uses the data segment register DS to provide the segment base. 2. The textbook symbol, indicating that the content can be omitted.

. LIST: pseudo-directives. Used to open the list file output.

. RADIX: pseudo-directive. Change the default cardinality to any cardinality in the range 2-16. The radix does not affect DD, DQ, DT pseudo-directives, in which the value entered is considered as a decimal number as long as the data type is not added.

. Xlist: pseudo-directive. Used to close the list file output.

%out: pseudo-directive. Displays subsequent information at the time of assembly.

AAA: Instruction Mnemonic--ASCII adjustment after addition operation (non-compressed BCD code). No operand, adjusted addition result in AL. The status change of AF and CF indicates that the result is greater than 9. Check if the low four bits of Al are valid BCD codes (0-9), and if valid, clear the high four bits of Al and the AF and CF flags. When Al's low four bits represent a number greater than 9 or af=1, the Al plus 6,ah plus 1 and AF and CF are set to clear the high four bits in AL. The number of any one a-f plus 6 will make Al low 4 bits produce a number between 0-9, thus achieving the purpose of the adjustment.

AAD: Instruction Mnemonic--the ASCII adjustment of the Division (non-compressed BCD code). Before you perform a division operation, you must convert the number of non-compressed BCD codes represented by the AAD instruction to the binary number to send al. The step is to first multiply the number of high points in the divisor (the contents of AH) by 10, then add to the low number of Al, and then clear the AH Zero.

AAM: Instruction Mnemonic--ASCII adjustment of multiplication (non-compressed BCD code). Used to convert the product of byte multiplication into two valid decimal non-compressed codes. AAM has no operands, assuming scores in Ah and AL, and sends the adjusted uncompressed code back to AH and al. To ensure that AAM obtains the correct results, the original multiplier and the multiplier must be valid non-compressed codes. When the instruction executes, AAM uses ten (0AH) in addition to the AL register, and sends the addition of the quotient and the remainder to the AH and the Al register respectively, to achieve the conversion.

AAS: Instruction Mnemonic--ASCII adjustment after subtraction (non-compressed BCD code). Check if the low four bits of Al are valid BCD codes (0-9), and if valid, clear the high four bits of Al and the AF and CF flags. When the lower four bits of Al represent a number greater than 9 or af=1, the Al minus 6,ah is reduced by 1 and the AF and CF are 1, and the high four bits in Al are cleared.

ADC: Instruction Mnemonic--with carry addition (the value of CF is added). A high-byte addition operation for multibyte numbers.

ADD: Instruction Mnemonic--addition. The two operands that participate in the operation should be signed or unsigned at the same time, with the same length. The operand can be a register, a memory, or an immediate number, but it cannot be a storage unit or segment register, and the number of immediate numbers cannot be used as the destination operand.

Af:auxiliary Carry flag, Secondary carry flag, 4th byte in the flag register. The Carry value (1) generated by the 3rd bit (half byte) when the operation is logged. This flag is used in the addition and subtraction operation of the BCD code.

And: A logical operator (in the part of the operand of a statement, at assembly time) or a logical operation instruction mnemonic (in the code portion of the statement, whose operation is done at the execution of the instruction)-bitwise AND. Only the two bits of the phase "and" are all 1, and the result is 1. Some number oneself with oneself phase "with", operand unchanged, carry mark CF clear 0.

Assume: Segment definition pseudo-directive--Sets the segment register in the format "assume segment Register: segment name [, Segment register Name: segment name]". The beginning of the code snippet is used to indicate the relationship of all segments to the segment register, and to determine which segment register a segment is assigned to. Assume only indicates the allocation of each segment register, and does not load the segment address into the corresponding segment register. To do this, in the code snippet, you must also load the segment address of the data segment and the additional data segment into the appropriate registers.

At: pseudo-directive--segment definition (combination type). The segment is positioned at absolute address, the segment base is the value of the numeric expression, and the displacement is 0. You cannot specify a code snippet.

Ax:accumulator, the General register, the main registers of arithmetic operations. In addition, all I/O directives use this register to transmit information to external devices. Where AH is 8 bits high, AL is low 8 bits.

B: Data type suffix, which represents a binary constant.

Bp:base Pointer, base point pointer register. Can be associated with the SS register to determine the address of any storage unit in the stack. It indicates the offset of any cell in the stack. Non-stack in and out instructions to access the stack, only through BP.

Bx:base, general purpose register. It is often used as a base address register when calculating memory addresses. Where BH is 8 bits high, BL is low 8 bits.

BYTE: Pseudo-directive--segment definition (anchor type). The starting unit of this paragraph can start from any address, without gaps between segments, the memory utilization is highest.

Call: Instruction Mnemonic--program invocation.
One, the direct call in the paragraph: The format is called procedure name. The IP content (the return address of the subroutine, the address of the next instruction of the call) is pressed into the stack, and then the IP is transferred to the subroutine's entry address.
Second, indirect invocation in paragraph: The format is "call WORD PTR OPD". The contents of the IP are first pressed onto the stack, and then the IP points (goes) to the EA determined by the addressing method.
Third, the direct call between paragraphs. The format is "call far PTR procedure name". First, the contents of CS and IP are pressed into the stack, then the new segment address is loaded in CS, and the IP points to the offset address within the segment.
Iv. indirect calls between paragraphs: The format is "call DWORD PTR OPD". The contents of CS and IP are pressed into the stack, and then the content of a word storage unit specified by the address method is determined to be sent to the IP, and the contents of the next Word storage unit (segment first address) are fed into CS.

CBW: Instruction Mnemonic--byte converted to Word. Expand the byte symbol in AL to AH, if the most significant bit of (AL) is 0, then (AH) = 00, or (AH) =0FFH if the most significant bit (AH) is 1.

Cf:carry flag, carry flag, in the No. 0 byte of the flag register, the carry value generated from the most significant bit when the operation is recorded (set 1). In addition, the CF bit can be used to denote an overflow of unsigned numbers (the number of symbols overflow in the representation of).

CLC: Instruction Mnemonic--flag (carry) setting. Set the cf=0.

CLD: Instruction Mnemonic--clear direction flag. Make df=0. Thus, the address automatically increases by 1 when executing the byte-string operation instruction, and the address automatically increases by 2 when the string operation instruction is executed.

CLI: Instruction Mnemonic--interrupt allow flag setting. Set the if=0.

CMC: Instruction mnemonic-flag (carry) setting. CF Inverse.

CMP: Instruction Mnemonic--comparison. For "CMP ax,bx", if it is two unsigned number comparison (minus), if the result does not produce borrow, that is cf=0, then (AX) ≥ (BX), if cf= 1, then (AX) (BX). If there is a two signed number comparison, if there is no overflow (of=0), if sf=0, (AX) (BX) If the sf=1, then (AX) (BX) when the overflow (of=1), if sf=0, then (AX) (BX) sf=1, then (AX) (BX) conciseness the conclusion, if of XOR or Sf=0 (AX) (BX) If of XOR or sf=1, then (AX) (BX)

CMPS: Instruction Mnemonic-string comparison. Usually with CMPSB or CMPSW.

CMPSB: Instruction Mnemonic-string comparison. The byte data indicated by the DS segment Si is subtracted from the byte data indicated by the ES segment Di (without saving the result), and then the flag bit is set according to the subtraction result (two data is equal, then zf=1). and by the direction Mark DF modifies the address in Si and Di, that is, when df=0, the address is added 1; When df=1, the address is reduced by 1.

CMPSW: Instruction Mnemonic-string comparison. The word data indicated by the DS segment Si is subtracted from the word data indicated by the ES segment Di (without saving the result), then the flag bit (two data equal, zf=1) is set according to the subtraction result. and by the direction Mark DF modifies the address in Si and Di, that is, when df=0, the address is added 2; When df=1, the address is reduced by 2.

COMMON: Pseudo-directive--segment definition (combination type). This section and all other modules are also described as common of the same name, with the ' category ' segment share the same storage area, that is, the starting address of these segments are the same, the length of the shared public storage area is the largest length of the same segment of the module. Use the common method to enable different variables or labels in different modules to act on the same storage unit.

Cs:code Segment, a code segment register that holds the starting address (high 16 bits) of the code snippet that is currently running. The code snippet holds the program that is currently running.

CWD: Instruction Mnemonic--word converted to double word. Expands the symbols for the bytes in ax into the DX, (dx) = 0000 If the most significant bit (AX) is 0, or (DX) =0FFFFH if the most significant bit (AX) is 1.

Cx:count, general purpose register. Used as an implied counter in loop and string processing directives. where CH is 8 bits high, CL is low 8 bits.

DAA: Instruction mnemonic--Decimal adjustment of addition (compressed BCD code). No operand, adjusted addition result in AL. The adjustment method is if the lower 4 bits of Al are greater than 9 or af=1, add 6 to the Al Af=1, and if the high 4 bits of Al are greater than 9 or cf=1, then add 60H to Al and place the cf=1.

DAS: Instruction mnemonic--decimal adjustment of subtraction (compressed BCD code). The adjustment method is that if the lower 4 bits of af=1 or Al are A-f, then (AL) minus 06H, and AF 1, if the Cf=1 or Al High 4 bits are a-f, then (AL) minus 60H, and CF 1.

DB: Pseudo-directive--defines bytes. Each subsequent operand occupies one byte. If the string must be enclosed in quotation marks, the string cannot exceed 255 characters, and the string is stored sequentially from left to right in the order in which the ASCII code of the character is incremented by the address.

DD: Pseudo-directive--define double word. Each subsequent operand occupies two characters (the lower word is in front). DD can also place the offset address of the subsequent variable or label and the first position of the segment into the specified double-word unit in memory (that is, the variable in front of DD), the first word holds the offset address of the variable after DD, and the second word holds the first address of the segment in which the variable is located.

DEC: Instruction mnemonic-minus 1. The operand can be a register or a memory unit, but not a segment register or an immediate number.

Df:direction flag, Direction flag, the 10th byte of the flag register, controls the direction of processing information in the string processing instruction. DF is the inverse of 1 o'clock, which makes Si and di decrement after each operation (so that the string processing is processed from the high address to the low address direction); When DF is positive for 0 o'clock, the SI and di increments are made.

Di:destination Index, Destination variable address register. Associated with ES, used to determine the offset address of a storage unit in a data segment. In the string processing instruction, di indicates the address of the destination operand, and the implied segment is the current additional segment.

DIV: Instruction Mnemonic--unsigned number division.
For byte operations, the 16-bit divisor (if the divisor is 8 bits, the method with the symbol extension, that is, extended to 16 bits with the CBW instruction) is placed in Ax, the 8-bit divisor is the source operand, the division result, 8 quotient in AL, and the 8-bit remainder in AH.
For word operations, the 32-bit divisor (if the divisor is 16 bits, extended to 32 bits with the CWD Directive) is placed in DX and AX, the 16-bit divisor is the source operand, the division result, the word (16-bit) quotient in Microsoft Dynamics AX, the word remainder in DX.
The source operand cannot be an immediate operand, and the value of the source operand does not change after the instruction executes.
If the quotient exceeds the maximum value that the target register can hold, the system generates 0 classes of interrupts.
Dividend if you need to convert to a double value, you must not use the symbol extension, but only the high 16 bits to send 0 ("MOV dx,0").

DQ: Pseudo-directive--defines four words. Each subsequent operand takes up to four characters.

Ds:data Segment, data segment register. The starting address for the data segment (16 bits high). The data segment holds the data used by the currently running program, and if a string processing instruction is used in the program, its source operand is also stored in the data segment.

DT: Pseudo-directive--defines 10 bytes. Each subsequent operand takes up to 10 bytes.

DUP: Copy operator. The value (positive integer) of the constant or expression preceding the DUP indicates the number of repetitions of the operand in parentheses following the DUP.

DW: Pseudo-directive--define word. Each subsequent operand occupies one word (low byte in front, high byte behind). DW can assign a two-character string (enclosed in ') to a two-byte storage unit (the previous character is in high-byte). The DW can also deposit the offset address of a subsequent variable or label into the specified unit of memory (the variable before the DW).

Dx:data, general purpose register. In the case of double-word operation, DX and AX are combined together to hold a double words, DX is used to store high-word. In addition, for some I/O operations, DX can be used to store I/O port addresses. Where DH is 8 bits high, DL is low 8 bits.

EA: The textbook symbol----The offset address of a storage unit, which is the byte distance from the cell to the first address of the segment.

ELSE: Pseudo-directive--condition. Assembly if the condition does not meet the block between the else and endif.

End: Pseudo-instruction-the end of the program module. The main program module ends and the end is followed by a label (memory address) indicating the address at which the program started executing. Subroutines are not used.

ENDIF: Pseudo-directive--condition (end).

ENDM: macro Directive--① macro definition (end). ② repeating block (end).

ENDP: Pseudo-directive--procedure (subroutine) definition (end).

ENDS: Pseudo-directive--segment definition or struct definition (end).

Es:extra Segment, additional segment register. The starting address for storing additional segments (high 16 bits). The additional segment is an auxiliary data area, and is also the purpose of the serial processing instruction to manipulate the data storage area.

ESC: Instruction Mnemonic--the right to the external coprocessor. is an instruction used in large mode that allows an external coprocessor to obtain an opcode and an operand from the 8086/8088 instruction stream and use 8086/8088 addressing. The opcode after the instruction is a 6-bit immediate number, where 3 bits are used to indicate which coprocessor is working, and the other 3 indicates what instructions the processor executes. If the subsequent source operand is a register, 8086/8088 directly places its contents on the data bus, and if the source operand is a storage variable, 8086/8088 takes the operand from the memory and puts it on the data bus so that the external coprocessor can get the operand and perform the operation on it.

EQ: Relational operators--equal. If the condition is met, the output is full 1 (all bits), otherwise all 0.

EQU: equivalent pseudo-directive. The format is "symbol name EQU expression". Equ can define the preceding symbol as a constant or an expression that can find a constant value, or define it as a different symbolic name or even an executable command. cannot be defined repeatedly.
Example one, "New variable name EQU this DWORD", which defines the variable immediately following it as a double-word class, named after the new variable name. The data store first address does not change.
Example two, "New variable name EQU WORD PTR old variable name", the statement redefined the old variable as a word type, named after the new variable name. The data store first address does not change.

Even: pseudo-directive. It causes the starting address of the program or data block after this statement to be an even number.

EXTRN: Pseudo-directive-defines an external symbol. The format is the EXTRN symbol name: type. Represents the symbols (symbolic constants, variables, labels, and procedure names) in this module that need to be referenced but are defined in other modules as public. Symbol types must be consistent with their symbol types when they are defined in other modules.

Flags: Flag register (that is, PSW).

GE: relational operator--greater than equals. If the condition is met, the output is full 1 (all bits), otherwise all 0.

Group: Pseudo-instructions--grouping. Set the segments of several different names in the module into a group and assign them to a group name so that they are all in one physical segment (64KB). A more compact code can be obtained, and jumps between segments within a group can be seen as jumps within a paragraph.
The format is group name, section name 1, segment Name 2, ... >

GT: relational operator--greater than. If the condition is met, the output is full 1 (all bits), otherwise all 0.

H: Data type suffix, which represents a hexadecimal constant.

High: Byte decomposition operator (operator). Used to isolate (fetch) high bytes from an operand (a number or address expression).

HLT: Instruction Mnemonic--stop. This instruction puts the processor in a paused state, which can be cleared by the reset signal, the unshielded interrupt request signal, and the if=1 interrupt signal.

Idiv: Instruction Mnemonic--signed number division.  For byte operations, the 16-bit divisor (if the divisor is 8 bits, the method with the symbol extension, that is, extended to 16 bits with the CBW instruction) is placed in Ax, the 8-bit divisor is the source operand, the division result, 8 quotient in AL, and the 8-bit remainder in AH.  For word operations, the 32-bit divisor (if the divisor is 16 bits, extended to 32 bits with the CWD Directive) is placed in DX and AX, the 16-bit divisor is the source operand, the division result, the word (16-bit) quotient in Microsoft Dynamics AX, the word remainder in DX. The symbol for the remainder must be the same as the dividend symbol.

If:interrupt Flag,① interrupt Flag, in the 9th byte of the flag register, when if is 1 o'clock, interrupts are allowed, that is, the CPU responds to the interrupt request of the peripheral. ② pseudo-directive--condition (the value of the expression is not equal to 0 is true). If the condition is set up, the entire block is compiled, but if there is an else command in the middle, it is compiled to else only, and when the condition is not true, only the blocks from else to endif are assembled.

IF1: pseudo-directive-condition (if the first scan, the condition is true).

IF2: pseudo-directive-condition (if two scan, the condition is true).

IFB: Pseudo-directive-the condition (true if the argument corresponding to the subsequent parameter exists).

Ifdef: pseudo-directive-condition (true if the symbol after it has been defined or is described as an external symbol).

IFDIF: pseudo-directive-condition (if two string arguments are different, the condition is true).

IFE: Pseudo-directive--condition (the value of the expression equals 0 o'clock, the condition is true).

IFIDN: pseudo-directive-condition (if two string parameters are the same, the condition is true).

IFNB: pseudo-directive-condition (true if the argument corresponding to the subsequent parameter does not exist).

IFNDEF: pseudo-directive-condition (if the symbol after it is undefined or not described as an external symbol, the condition is true).

Imul: Instruction Mnemonic--signed integer multiplication.   For byte multiplication, (AL) * (source operand)---> AX;   For word multiplication, (ax) * (source operand)---> AX and DX; If the high half of the result (ah or DX, corresponding byte and word) is the lower half of the symbol extension, then cf=0,of=0; otherwise, cf=1,of=1, which represents a valid value that contains the result in AH (for bytes) or DX (for words).

In: Instruction mnemonic--input. Allows a word or byte to be transferred to Ax or Al by the input port. The port address can be directly addressed (in AL N), and DX indirection (in AL,DX) is also available. 8-bit address direct addressing, 256 ports addressable, DX indirect addressing, 64K ports addressable.

INC: Instruction Mnemonic--plus 1. The operand can be a register or a memory unit, but not a segment register or an immediate number. The status flag CF is not affected.

INCLUDE: pseudo-directive. When the macro assembler is assembled into the include pseudo-directive, open the file with the include directive immediately and assemble it into the current source file until the file is assembled and the assembler continues to assemble the statements that include the pseudo-directives. Include can be nested.

INT: Instruction Mnemonic--interrupt invocation. The operand is a user-defined interrupt type that can achieve 256 different interrupts. When the instruction executes, the flag register contents are first put into the stack, the IF and TF flags are cleared and the current CS content is stacked, then the interrupt type is multiplied by 4 to get the interrupt vector address, the second word of the interrupt vector is sent to CS, the IP is sent to the stack, and the first word of the interrupt vector is taken. Because Cs:ip points to an interrupt service program, you can implement inter-segment calls that specify break types.

into: Instruction mnemonic-overflow interrupt. Overflow interrupts are only entered when of=1 (if and TF are changed to 0).

Ip:instruction Pointer, control register--instruction pointer register. The offset address used to hold the instruction in the code snippet. During a program's run, it always points to the first address of the next instruction. It is associated with CS to determine the physical address of the next instruction to be executed. The IP register cannot be used for arithmetic operations and cannot be accessed directly, but can be changed with control transfer directives.

IRET: Instruction Mnemonic--interrupt return. When executing the instruction, exit three 16-bit values from the stack, sending the IP, CS, and flag registers separately.

IRP: Macro--repeating block (ends with ENDM). IRP parameter, argument 1, argument 2, ... This macro is used for pseudo operations with immediate numbers. An argument is a user-specified immediate number, the number of which is the number of repetitions, each repetition, with an argument instead of a formal parameter.

IRPC: Macro--repeating block (ends with ENDM). A irpc parameter, a string that is used for repeating pseudo-operations with strings. The number of repetitions is determined by the number of characters in the string. Each time you repeat, replace the formal parameter with one of the characters in the string until the character substitution is complete.

JA: Unsigned number conditional transfer instruction mnemonic-(unsigned number comparison) is higher than transfer (equivalent Jbe). Cf=0, and the zf=0 is transferred (direct short transfer within the segment).

JAE: Unsigned number conditional transfer instruction mnemonic-(unsigned number comparison) is higher or equal to transfer (equivalent JNB). Cf=0, or zf=1 transfer (direct short transfer within the paragraph).

JB: Unsigned number conditional transfer instruction mnemonic-(unsigned number comparison) is lower than transfer (equivalent Jnae). Cf=1, and the zf=0 is transferred (direct short transfer within the segment).

Jbe: Unsigned number conditional transfer instruction mnemonic-(unsigned number comparison) less than or equal to transfer (equivalent JNA). Cf=1 or zf=1 are transferred.

JC: Simple Conditional transfer instruction mnemonic--there is a carry transfer. The cf=1 is transferred (a direct short transfer within the segment, resulting in a 8-bit displacement, i.e. the offset of the transfer address between 128 and +127).

JCXZ: Instruction mnemonic-conditional transfer. (CX) = 0, then transfer (direct short transfer within paragraph) )。

JE: Simple Conditional transfer instruction mnemonic-(two-number comparison) equal transfer (same as JZ). The result of the previous operation is 0,zf=1 (direct short transfer within the segment).

JG: Signed number conditional transfer instruction mnemonic--(signed number comparison) is greater than transfer (equivalent Jnle). SF and of the same number, and zf=0 when transferred. (Direct short transfer within paragraph)

JGE: Signed number conditional transfer instruction mnemonic-(signed number comparison) greater than or equal to transfer (equivalent to Jnl). When SF and of of the same number, or zf=1, then transfer (within the paragraph direct short transfer).

JL: Signed number conditional transfer instruction mnemonic--(signed number comparison) less than transfer (equivalent to Jnge). When SF and the of the Zf=0 are transferred (the direct short transfer within the segment).

Jle:

The instruction mnemonic-(signed number comparison) is less than or equal to the transfer (equivalent to Jng). When SF and of the XOR or zf=1 are shifted (the direct short transfer within the segment).

JMP: Instruction mnemonic-unconditional transfer. Unconditionally transfers to the destination address indicated by the instruction and executes from that address. The destination address can be obtained directly from the instruction, or from a register or memory given in the instruction.
Transfer the short label directly in JMP within a paragraph. The label is the destination address of the transfer, which determines the amount of a 8-bit displacement. This amount of displacement is added to the IP register. The displacement amount is a signed number, negative numbers indicate a forward transition, and positive numbers indicate a backward transition. The transfer range is 128 to +127.
In the second paragraph, the direct transfer of JMP near PTR label. The label is the destination address of the transfer, which determines the amount of a 16-bit displacement. This amount of displacement is added to the IP register. The displacement amount is a signed number, negative numbers indicate a forward transition, and positive numbers indicate a backward transition. The transfer range is 32768 to +32767.
Third, the indirect transfer ①jmp AX (intra-segment register indirect transfer); ②jmp [BX] (Intra-segment memory indirect transfer). Sends the contents of the specified register or storage unit in the instruction to the IP.
Direct transfer of JMP far PTR designator between paragraphs. The label is the symbolic address.

JNB: Unsigned number conditional transfer instruction mnemonic-(unsigned number comparison) not less than transfer (equivalent Jae). Cf=0, or zf=1 transfer (direct short transfer within the paragraph).

Jnbe: Unsigned number conditional transfer instruction mnemonic-(unsigned number comparison) is not less than and not equal to transfer (equivalent JA). Cf=0, and the zf=0 is transferred (direct short transfer within the segment).

JNC: Simple Conditional transfer instruction mnemonic--previous operation No in or carry bit transfer. Cf=0 is transferred (direct short transfer within paragraph).

JNE: Simple Conditional transfer instruction mnemonic-unequal transfer (same as JNZ). The result of the previous operation is not equal to 0,zf=0 (direct short transfer within the segment).

JNG: The instruction Mnemonic-(a signed number comparison) is not much more than a transfer (equivalent to JLE). When SF and of the XOR or zf=1 are shifted (the direct short transfer within the segment).

Learn the assembly instructions that the Linux kernel often encounters (1)

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