Linux-driven PCI

< background >

The PCI device has many address configuration registers, which are initialized to configure the device's bus address, and the CPU can access the resources of the device when it is configured. (Refine: Configure bus address)  < Configuration register >  (1) 256-byte PCI configuration space is divided into 64-byte header areas and 192-byte device-dependent areas. Each register in the header area is used to uniquely identify the device, and the relevant area of the device stores some device-related data. (2) The header area of the configuration space is divided into two parts: the first 16 byte definitions are the same in all types of PCI devices; the remaining bytes vary depending on the device type. The header Type field at offset address 0EH Specifies the layout structure of the header area. Currently, the specification defines three types of header labels.                               &NBSP;A: Equipment Identification (1)   Supplier code: This register is used to identify the manufacturer of the PCI device, and the specific code is assigned by the PCI SIG (http://www.pcisig.com). 0FFFFH is an invalid vendor code. (2)       device code. This register is used to identify the specific equipment produced by a vendor, and the code is defined by each vendor. The supplier code and the device code, the reader can go to the website http://www.pcidatabase.com/consult. (3)       version number. This register is used to define the version information for the specified device. (4)       header type. The 7th digit of the field is "1" to identify the device as a multifunction device and a "0" as a single-function device; the 0~6 bit of the field is the header type described in the table above. (5)       equipment classification code. Used to identify the overall functionality of the device and a specific register-level programming interface. All 5 of the above fields are read-only, and all PCI devices must implement their capabilities. B: Device control and Device status (1)       Command Register provides coarse control for a device to emit and respond to a PCI bus command. Figure 4 is the command register format.   bit 0 (I/O space control): Controls the response to I/O space access. This bit is 0 o'clock and prevents the device from responding to access to I/O space, which is 1 o'clock, which allows the device to respond to I/O space access. The default setting is 0. Bit 1 (Memory space Control): Controls a setThe response to memory space access. The bit is 0 o'clock, the response is forbidden, and the bit is 1 o'clock, allowing the device to respond to access to the memory space. The default setting is 0. The   status register is used to record the status information about the PCI bus. C: Base register PCI device, in addition to the configuration space, there are two physical space: memory space and I/O space. In order to access these two address spaces, the base register must be used. Header type 0 involves 3 base address registers: the memory space Base register, the I/O space base Register, and the extension ROM base register. D: Other Registers

 

Other registers include registers that are not covered in this article, such as interrupt pins, middle wire breaks, and so on. The Access >    A:PCI specification for the &NBSP;&LT;PCI configuration space uses 8 I/O addresses from 0CF8H~0CFFH to access the PCI configuration space for all devices. These 8 bytes actually constitute two 32-bit registers: The 0CF8H register is called the "Configuration address register", and the 0CFCH is called "Configuration data Register". When you want to access a register for a configuration space, you write the destination address to the address register, and then you can read and write data from the data register. The        &NBSP;PCI configuration space corresponds to a PCI logical device, so to access a register for a configuration space, you must specify: PCI bus number, PCI device number, PCI device function number, and register number. The format of the address register is as follows:                             NO. 0, 1 digits The "0" is used to require you to read and write the configuration space register only by double Word (4 bytes). The 31st bit, enable bit, is used to determine whether access to the configuration space is allowed: "1" means that it is accessible, and "0" indicates that it is not accessible.         from the format of the above configuration address register we can see: Bus number from 0~255, device number from 0~31, function number from 0~7. Determine if the PCI device is present based on whether the No. 0 register in the configuration space returns a value of 0FFFFH (it can be seen that PCI supports 32 devices) &NBSP;&LT;PCI Driver Development Overview > for driver developers, PCI has the following attractive advantages: a: Device Autoconfiguration System, unlike the old ISA driver, PCI drivers do not need to implement complex detection logic. B: When the system starts, the BIOS (if it is the embedded system core itself) will traverse the PCI bus and allocate resources (such as interrupt priority, I/O base address)  c:  device Go driver will query memory called "PCI configuration Space" to find resource allocation D: PCI devices have a total of 256B of configuration space memory. The meaning of 64B space at the top of the configuration space is standard, and the configuration of all devices is similar in this area. The space is divided into state, I/O base address, and disconnected.  < Access Pci>a: Kernel function Pci_read_config_[byte|word|dword] (STRuct Pci_dev *pdev,int offset,int *value) Pci_write_config_[byte|word|dword] (struct Pci_dev *pdev,int offset,int *value ) parameter analysis: Pdev: The structure of the PCI device offset: Offset address of the configuration space value: the location where the data needs to be written or read example: unsigned char irq;pci_read_config_byte (pdev,pci_ INTERRUPT_LINE,&AMP;IRQ); Note: The offset of the interrupt number in the configuration space is 60, which is why 60 is not used, because/include/linux/pci_regs.h is defined in the Linux kernel. &NBSP;&LT;I/O and Memory >i/o access a: The mapping of a PCI device's I/O space or memory space in memory or I/O area. The base address of the I/O region is obtained from the corresponding base-site register that needs to read the configuration space. (1) The base address of the I/O region is obtained from the corresponding base register of the configuration area unsigned long io_base = Pci_resource_start (pdev,bar) Note: The function also has a corresponding transformation unsigned long pci_ Resource_[start|lenght|flags] (struct pci_dev*pdev, int bar) (2) Call the kernel function request_region () to obtain this IO area, indicating the device corresponding to this area Request_ Region (Io_base,length, "Mydriver") (3) This allows access to these registers with the I/O operation function, INL (); Outl ();
Memory Access (1) Call this function to get the memory base address unsigned long pci_resource_[start|lenght|flags] (struct pci_dev*pdev, int bar) (2) Call the kernel function request_ Mem_region () Obtains this memory area, indicating that this area corresponds to the device request_region (mmio_base,mmio_length, "Mydriver") (3) will obtain the memory address converted to the virtual address buffer = Pci_ Iomap (Pdev, bar,mmio_length) < driver instance >a when PCI HotPlug detects the id attribute of the newly inserted device and the ID information of the pci_device_id table in the driver is consistent. The layer will fire the driver's probe () function to be called. Further register the appropriate device drivers. You can see that you first have to register the Pci_driver program: Call function Pci_register_drivet () B:

Linux-driven PCI