Linux Makefile Tutorial Writing command four [go]

Writing commands
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The commands in each rule are consistent with the command line of the operating system shell. Make will execute a command in a sequential order, and each command must begin with the [Tab] key, unless the command is immediately followed by a semicolon following the dependency rule. Spaces or empty rows between the command lines are ignored, but if the space or blank line starts with the TAB key, make considers it to be an empty command.

We might use a different shell under Unix, but the make command is executed by default by the standard shell interpretation of "/bin/sh"--unix. Unless you specifically specify a different shell. In Makefile, "#" is an annotation, much like "//" in C + +, after which the line characters are commented.

First, show the command

Typically, make prints the command line it executes to the screen before the command executes. When we use the "@" character at the command line, then this command will not be shown by make, the most representative example is that we use this function to display some information like a screen. Such as:

@echo is compiling the XXX module ...

When make executes, the "Compiling XXX module ..." string is output, but the command is not output, and if there is no "@", make will output:

echo is compiling the XXX module ...
Compiling XXX module ...

If make executes, bringing in the Make parameter "-n" or "--just-print", then it just shows the command, but does not execute the command, this function is good for us to debug our makefile, to see what we write the command is to execute what is the appearance or in what order.

The Make parameter, "-S" or "--slient", is a full-ban display of commands.



Ii. Execution of Orders

When a dependent target is new to the target, that is, when the target of the rule needs to be updated, make makes a single command that executes thereafter. Note that if you want to apply the results of the previous command to the next command, you should separate the two commands with semicolons. For example, your first command is a CD command, you want the second command to run on the basis of the CD, then you cannot write these two commands on two lines, but should write the two commands on one line, separated by semicolons. Such as:

Example one:
Exec:
Cd/home/hchen
Pwd

Example two:
Exec:
Cd/home/hchen; Pwd

When we execute "make exec", the CD in the first example does not work, the PWD prints out the current makefile directory, and in the second case the CD works, the pwd prints "/home/hchen".

Make generally executes commands using the system shell defined in the environment variable shell, and by default uses the UNIX standard shell--/bin/sh. But it's a bit special in MS-DOS, because there's no shell environment variable under MS-DOS, and of course you can specify. If you specify a UNIX-style directory format, first, make will look for the command interpreter in the path specified by the shell, and if not, it will be found in the current directory in the current disk, and if it is not found, it will look in all paths defined in the PATH environment variable. In MS-DOS, if you define a command interpreter that is not found, it will give you a command interpreter with suffixes such as ". exe", ". com", ". Bat", ". Sh", and so on.


Third, the command error

Whenever the command finishes, make detects the return code of each command, and if the command returns successfully, then make executes the next command, and when all the commands in the rule return successfully, the rule is completed successfully. If a command in a rule goes wrong (the command exit code is not 0), then make terminates execution of the current rule, which is likely to terminate execution of all rules.

Sometimes, an error in a command does not mean that it is wrong. For example, mkdir command, we must create a directory, if the directory does not exist, then mkdir successfully executed, all right, if the directory exists, then the error. The reason we use mkdir means that we must have such a directory, so we do not want to mkdir error and terminate the operation of the rule.

In order to do this, ignoring the command error, we can add a minus "-" (after the TAB key) to the command line of the makefile and mark it as successful regardless of the command error. Such as:

Clean
-rm-f *.O

There is also a global way to add "-I" or "--ignore-errors" parameters to make, then all the commands in makefile will ignore the error. And if a rule is to ". IGNORE "as the target, then all commands in this rule will ignore the error. These are different levels of methods for preventing command errors, which you can set according to your preferences.

Another way to mention the make parameter is "-K" or "--keep-going", which means that if a command in a rule goes wrong, the rule is executed, but the other rules are executed.



Iv. Nesting execution make

In some large projects, we will put our different modules or different functions of the source files in different directories, we can write a directory in each directory of the makefile, which helps to make our makefile become more concise, Rather than writing everything in one makefile, it's hard to maintain our makefile, a technique that has great benefits for our module compilation and staging.

For example, we have a subdirectory called SubDir, which has a makefile file that indicates the compilation rules for the files in this directory. So the makefile that we have always controlled can write like this:

Subsystem
CD SubDir && $ (make)

It is equivalent to:

Subsystem
$ (make)-C subdir

The definition of the $ (make) macro variable means that perhaps our make requires some parameters, so defining a variable is more conducive to maintenance. These two examples are all meant to go into the "subdir" directory and then execute the make command.

We call this makefile "Master Makefile", and the makefile variable can be passed to the subordinate makefile (if you display the declaration), but will not overwrite the variable defined in the underlying makefile unless the "-E" parameter is specified.

If you want to pass a variable to a subordinate makefile, you can use such a declaration:

Export <variable ...>

If you do not want certain variables to be passed to the subordinate makefile, you can declare this:

Unexport <variable ...>

Such as:

Example one:

Export variable = value

It is equivalent to:

Variable = value
Export variable

It is equivalent to:

Export variable: = value

It is equivalent to:

Variable: = value
Export variable

Example two:

Export variable + = value

It is equivalent to:

Variable + = value
Export variable

If you're going to pass all the variables, just one export is OK. You don't have to follow anything, it means passing all the variables.

Note that there are two variables, one is the shell, the other is makeflags, the two variables regardless of whether you export, it is always passed to the lower makefile, especially the makefiles variable, which contains the parameter information of make, if we execute " Total Control Makefile "when there is a make parameter or defined in the upper makefile, then the makefiles variable will be these parameters and will be passed to the lower makefile, which is a system-level environment variable.

However, there are several parameters in the make command that are not passed down, they are "-C", "-F", "-H", "-O" and "-W" (Details about the makefile parameter will be explained later), if you do not want to pass the parameter down, then you can:

Subsystem
CD SubDir && $ (make) makeflags=

If you define the environment variable makeflags, then you have to be sure that the options are used by everyone, if there are "-T", "-N", and "-Q" parameters, then there will be unexpected results, you may be abnormal panic.

There is also a parameter that is useful in "nested execution", and "-w" or "--print-directory" will output some information during make to allow you to see the current working directory. For example, if our subordinate make directory is "/home/hchen/gnu/make", if we use "make-w" to execute, then when we enter the directory, we will see:

make:entering directory '/home/hchen/gnu/make '.

When you leave the directory after you complete the downlevel make, we see:

make:leaving directory '/home/hchen/gnu/make '

When you use the "-C" parameter to specify make downlevel Makefile, "-W" is automatically opened. If the parameter has "-S" ("--slient") or "--no-print-directory", then "-w" is always invalidated.



V. Defining command Packages

If some of the same command sequences appear in Makefile, then we can define a variable for these same command sequences. The syntax for defining this sequence of commands begins with "define" and ends with "endef", such as:

Define RUN-YACC
YACC $ (FirstWord $^)
MV Y.TAB.C [email protected]
Endef

Here, "Run-yacc" is the name of this command package, not the same as the variable in makefile. The two lines in "define" and "endef" are command sequences. The first command in this command package is to run the YACC program, because the YACC program always generates "Y.TAB.C" files, so the second line of the command is to change the name of the file. Let's take a look at the command pack in an example.

Foo.c:foo.y
$ (RUN-YACC)

We can see that to use this command package, we are like using variables. In the use of this command package, the command package "RUN-YACC" in the "$^" is "foo.y", "[e-mail protected]" is "foo.c" (about this special variable with "$", we will describe later), make when executing the command package, Each command in the command pack is executed independently.