Linux system Timing

The 8253 is used in IBM PC compatibles since their introduction in 1981. [1] in the modern times, this PIT was not included as a separate chip in an x86 PC. Rather, its functionality are included as part of the motherboard ' s Southbridge chipset. In some modern chipsets, this change could show up as measurable timing differences in accessing a PIT using the x86 I/O add Ress space. Reads and writes to such a PIT ' s registers in the I/O address space may complete much faster.

Newer motherboards also include a counter through the advanced Configuration and Power Interface (ACPI), a counter on the Local Advanced Programmable Interrupt Controller (local APIC), and a high Precision Event Timer. The CPU itself also provides the time Stamp Counter (TSC) facility.

From

The timer has three counters, called channels. Each channel can is programmed to operate in one of six modes. Once programmed, the channels can perform their tasks independently. The timer is usually assigned to IRQ-0 (highest priority hardware interrupt) because of the critical function it performs And because so many devices depend on it. [

From

Linux system Timing