Linux Interrupt Subsystem

I. Overview

1. Objective

Kernel How to manage hardware devices: polling, interrupts. Interrupt efficiency is high and the response is faster than polling because it takes advantage of the ' interrupt signal cycle polling ' that is done before the hardware itself executes the instruction.

1. Classification

Interrupts are divided into synchronous (synchronous) and asynchronous (asynchronous).

Synchronization is also known as an exception, generated by a CPU instruction error, divided into fault, trap and abort;

Asynchronous, also known as interrupts, is generated by external electrical signals, and is divided into x86 (INTR) and unshielded interrupts (NMI) for ARM, and IRQ and Fiq for arms;

For x86 CPUs, there are two interrupt input pin:intr and NMI. When the CPU receives a INTR interrupt, it is answered by the INTA pin, indicating that the interrupt was received

1. Interrupt controller: PIC, APIC, and GIC

Pic–programmable Interrupt Controllers programmable Interrupt Controller (x86 up)

apic–advanced Programmable Interrupt Controller Advanced Programmable Interrupt controllers (X86MP)

Gic–generic Interrupt controller arm designed for general purpose interrupt controllers (MP support)

View through Cat/proc/interrupts.

Up:uni-processor (single core); Mp:multiple-processor (multicore).

1. Other

Second, initialize

Third, the processing process

Iv. API

V. Questions

How do you design the interrupt controller in the system with 8 CPUs and 2000 peripheral interrupts to handle? (using GIC and APIC)

Vi. Other

Linux Interrupt Subsystem