Linux interrupts and system calls & ESP, EIP and other registers

Http://www.linuxidc.com/Linux/2012-11/74486.htm

Altogether three articles

Interrupts are generally divided into three categories :

1, by the computer hardware abnormal or failure caused by the interruption, called internal abnormal interruption;

2, the interrupt caused by the execution of the instruction in the program is called Soft Interrupt (which is also the interrupt related to the system call we will describe);

3. Interrupts caused by external device requests are called external interrupts. In short, the understanding of interruptions is the handling of some special things.

When a software outage occurs, all other interrupts can occur and are processed, but when a disk outage occurs, only clock interrupts and machine error interrupts can be processed.

What is the difference between a user state and a nuclear mindset? (The following distinctions are taken to the UNIX operating system design)

1, the user-state process can access their own instructions and data, but not access to the kernel instructions and data (or other process instructions and data). However, processes in the nuclear mindset can access the kernel and user addresses

2, some machine instructions are privileged instructions, the execution of privileged instructions under the user state will cause errors

One understanding of this is that in the system the kernel is not a collection of processes that are parallel to the user process, and the kernel is running for the user process.

The kernel's own stack is in the top-level 1G address space, which is the only part that is accessible by the kernel.

Http://www.cnblogs.com/txlstars/p/5401033.html

User state: Ring3 the code running in the user state is subject to many checks by the processor, which can only access the virtual address of the page that is specified in the page table entry that maps its address space, and only the I/O license bitmap in the task status segment (TSS) (I/O Permission BITMAP) provides direct access to the accessible ports specified in the

Kernel state: RING0 in the storage protection of the processor, the kernel mentality, or the privileged state (which corresponds to the user state), is the mode that the operating system core runs. Code running in this mode allows unrestricted access to system storage and external devices.

Second, under what circumstances will occur from the user state to the kernel state switch. There are 3 different cases.

1 ,      This is a way for the active request of a process that is in the user state to switch to the kernel state when a system call occurs. The user-State process requests the system invoke service routines provided by the operating system to process the task using the systems call. And the mechanism of system invocation, the core of which is still the use of the operating system for the user specifically developed an interrupt mechanism to achieve, that is, soft interrupt.  2. When an exception occurs when the      CPU executes a program running in the user state, some of the pre-unknown exceptions are triggered by the current running process switching to the kernel-related program that handles the exception, that is, to the kernel state, such as a page fault.  3, peripheral interrupt when the      peripheral device completes the user requested operation, the CPU will be issued a corresponding interrupt signal, then the CPU will suspend execution of the next command to execute the order to execute the processing program corresponding to the interrupt signal, If the previously executed instruction is a user-state program, then the process of the conversion will naturally occur from the user state to the kernel state switch. such as the completion of the hard disk read and write operation, the system will switch to the hard disk read and write interrupt handler to perform subsequent operations.           you can see that the above three kinds of user-state switching to the kernel state, only the system call is the process of active request switching, interrupts and exceptions are passive . 

Specific switching operations , the key steps involved are exactly the same, without any difference.

The steps involved in switching from a user state to a kernel state include:

[1] Extracts the SS0 and esp0 information of its kernel stack from the descriptor of the current process.

[2] using SS0 and esp0 point to the kernel stack to save the current process CS,EIP,EFLAGS,SS,ESP information, the process also completed by the user stack to the kernel stack switching process, while saving the suspended execution of the program's next instruction.

[3] The CS,EIP information of the interrupt handler that was previously retrieved by the interrupt vector is loaded into the appropriate register, and the interrupt handler is executed, and then the program of the kernel state is executed.

About ESP, EIP

http://blog.csdn.net/chenlycly/article/details/37912417

1.EIPThe register stores the address of the next instruction to be executed by the CPU. That is, after the fun function is called, let the CPU know that the printf ("End of Function call") statement in the main function should be executed. 2.EBPThe register is stored in the stack of the stack of pointers, usually called the stack base, this is the beginning of the fun () function call, passed to the EBP by esp. (You can understand this before the function call: ESP stores the top and bottom addresses.) ) 3.ESPThe register stores the stack top of the stack after calling the function fun (). And always point to the top of the stack. At the end of the call, EBP will return the address back to esp. So once again, esp points to the address of the top of the stack after the function call ends. More aboutRegister DeviceThe content that needs to see here: http://blog.csdn.net/chenlycly/article/details/37912683

4 Data registers (EAX, EBX, ECX, and edx)
2 variable address and pointer registers (ESI and EDI) 2 pointer registers (ESP and EBP)
6 segment Registers (ES, CS, SS, DS, FS and GS)
1 instruction Pointer Register (EIP) 1 flag Register (EFLAGS)

The 32-bit CPU has 4 general-purpose registers of 32-bit eax, EBX, ECX, and edx. Access to low 16-bit data does not affect data that is 16 bits high. These
The low 16-bit registers are named: AX, BX, CX, and DX, which match the registers in the previous CPU.

Registers Ax and Al are often called accumulators (accumulator), and operations with accumulators may take less time. Accumulators can be used to multiply,
In addition, input/output and other operations, they are very high frequency of use;
The register BX is called the base register. It can be used as a memory pointer;
The register CX is called the Count register. It is used to control the number of loops during loop and string manipulation.
, when moving multiple bits, it is necessary to use CL to indicate the number of displaced bits;
The register DX is called the data register. It can participate in the operation as the default operand when the multiply, divide operation is performed, or
The port address that can be used to hold I/O.

2. Variable address register

The 32-bit CPU has 2 32-bit general-purpose registers ESI and EDI. They are primarily used to store the offset of the storage unit within the segment,
They can be used to address a variety of memory operations, providing convenient access to storage units in different addresses.

Segment registers inside the CPU:

cs--Code Segment Register, whose value is the segment value of the code snippet;
ds--Data Segment Register, whose value is the segment value of the data segment;
es--Additional segment Register (Extra Segment register), whose value is the segment value of the additional data segment;
The ss--stack segment register (stack Segment register), whose value is the segment value of the stack segment;
fs--Additional segment Register (Extra Segment register), whose value is the segment value of the additional data segment;
The gs--additional segment register (Extra Segment register), whose value is the segment value of the additional data segment.

Linux interrupts and system calls & ESP, EIP and other registers