Linux Memory Management Learning 3--head. The establishment of the section page table in S

Author

Pengdonglin

[Email protected]

Platform

TQ2440

Qemu+vexpress-ca9

Linux-4.10.17

Body

Continue analyzing head. S

1Ldr R13, =__mmap_switched @ address to jump2 @ MMU has been enabled3Badr LR, 1f @return(PIC) address4mov r8, r4 @SetTTBR1 to Swapper_pg_dir5 Ldr R12, [R10, #PROCINFO_INITFUNC]6 add R12, R12, R107 ret R128 1: b __enable_mmu

The 1th line assigns the virtual address of the __mmp_switched label to R13, which is used when the back is returned from __turn_mmu_on .

The 3rd line assigns the physical address of the 1f label to LR, which is used when returned from __arm920_setup.

The 4th line is to assign the physical starting address of the Segment page table to R8, which is 0x3000_4000 for TQ2440, 0x6000_4000 for vexpress

Line 5th, because R10 points to the first address of the matching proc_info_list struct, for TQ2440, the offset #PROCINFO_INITFUNC get __arm920_setup and __ARM920_PROC_ Info of the difference, stored in the R12, at this time R10 storage is __arm920_proc_info Physical address

Line 6th, R10 plus R12 get __arm920_setup Physical address, for Vexpress is __v7_ca9mp_setup

Line 7th, start execution __arm920_setup, defined in arch/arm/mm/proc-arm920. S medium

1 . Type __arm920_setup, #function2 __arm920_setup:3mov r0, #04MCR P15,0, R0, C7, C7 @ Invalidate I,d caches on V45MCR P15,0, R0, C7, C10,4@ Drain Write buffer on V46 7MCR P15,0, R0, C8, C7 @ invalidate i,d tlbs on v48 9 ADR R5, Arm920_crvalTen Ldmia R5, {R5, R6} OneMRC P15,0, R0, C1, C0 @GetControl Register V4 A Bic R0, R0, R5 - Orr R0, R0, R6 - ret LR the. Size __arm920_setup,. -__arm920_setup -  -     /* - * R +      * . RVI Zfrs BLDP Wcam -      * .. 11 0001.. 0101 +      *  A      */ at. Type Arm920_crval, #Object - Arm920_crval: -Crval clear=0x00003f3f, mmuset=0x00003135, ucset=0x00001130

This function performs some preparatory work before opening the MMU. The above operation of the cache, TLB can refer to the manual arm920t Technical Reference Manual 2.3.11 Register 7, Cache Operations Register and 2.3.12 Register 8, TLB Operations Register

When the 14th line is finished, it jumps to the head that was mentioned earlier. The 1f label in S, which is b __enable_mmu

For the operation of the MMU, refer to the manual arm920t Technical Reference Manual 2.3.5 Register 1, control register

Back to head. s continues the analysis.

1 __enable_mmu:2 #ifDefined (config_alignment_trap) && __linux_arm_arch__ < 63 Orr R0, R0, #CR_A4 #else5 Bic r0, r0, #CR_A6 #endif7 8 mov R5, #DACR_INIT9MCR P15,0, R5, C3, C0,0@ Load Domain Access RegisterTenMCR P15,0, R4, C2, C0,0@ Load Page table pointer One  Ab __turn_mmu_on

The 10th line of the physical starting address of the section table is set to the C2 register of CP15, i.e. 0x30004000 or 0x60004000, which can refer to arm920t Register 2 Technical Reference Manual 2.3.6, Translation table base (TTB) register

Line 12th, ready to open the MMU.

Now open the MMU:

1. align52. pushsection. Idmap.text,"Ax"3 ENTRY (__turn_mmu_on)4 mov r0, r05 Instr_sync6MCR P15,0, R0, C1, C0,0@ Write Control reg7MRC P15,0, R3, C0, C0,0@ Read ID reg8 Instr_sync9 mov R3, R3Ten mov r3, R13 One RET R3 A __turn_mmu_on_end: - Endproc (__turn_mmu_on) -. popsection

The 6th line opens the MMU, so the program can continue execution without error because the section table that mapped this part has been established before

Line 10th, the virtual address of __mmap_switched is stored in the R13.

Line 11th, start jumping to __mmap_switched, since then the virtual address is the same as the link address

__mmap_switched defined in Arch/arm/kernel/head-common. S in:

1 __mmap_switched:2 ADR R3, __mmap_switched_data3 4Ldmia r3!, {r4, R5, R6, R7}5CMP R4, R5 @ Copy data segmentifneeded6 1: Cmpne R5, R67Ldrne FP, [R4], #48Strne FP, [R5], #49 BNE 1bTen  Onemov fp, #0@ Clear BSS (and zero FP) A 1: CMP R6, R7 -STRCC FP, [r6],#4 - BCC 1b the  - ARM (Ldmia R3, {r4, R5, R6, R7, SP}) -  - str R9, [R4] @ Save processor ID + str R1, [R5] @ Save Machine type - str R2, [R6] @ Save atags pointer +CMP R7, #0 A Strne r0, [R7] @ Save control Register Values at b start_kernel - Endproc (__mmap_switched) -  -. align2 -. Type __mmap_switched_data,%Object - __mmap_switched_data: in.Long__data_loc @ R4 -.Long_sdata @ R5 to.Long__bss_start @ r6 +.Long_end @ R7 -.Longprocessor_id @ R4 the.Long__machine_arch_type @ R5 *.Long__atags_pointer @ r6 $.Longcr_alignment @ R7Panax Notoginseng.LongInit_thread_union +thread_start_sp @ SP -. Size __mmap_switched_data,. -__mmap_switched_data

Here is the main focus on the 16th to 23rd Line, where the R9 stored in the CPU ID assigned to processor_id, DTB the Physical address assigned to __atags_pointer, Set the SP to Init_thread_union + thread_start_sp, where init_thread_union is defined in INIT/INIT_TASK.C, the value of THREAD_START_SP is (8KB-8), This is the kernel stack that the SP points to the Init process. Then line 23rd jumps to the Start_kernel in INIT/MAIN.C.

Finish.

Linux Memory Management Learning 3--head. The establishment of the section page table in S