Linux/unix environment of make and makefile detailed _unix Linux
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Make and makefile detailed in Linux/unix environment
Make is a very important compilation command, both in Linux and in UNIX environments. Whether you are developing your own projects or installing applications, we often use make or make install. With make tools, we can break down large development projects into more manageable modules, and for an application that includes hundreds of source files, using make and makefile tools, you can succinctly and concisely streamline the complex interrelationships between the various source files. And so many source files, if you have to type the GCC command to compile each time, it would be a disaster for programmers. The Make tool automates compilation and can compile only those parts of the programmer that have been modified since the last compilation. Therefore, effective use of make and makefile tools can greatly improve the efficiency of project development. At the same time master make and makefile, you will not be faced with Linux under the application of software helpless.
Unfortunately, in many books on Linux applications, this powerful but very complex compilation tool is not covered in detail. Here I will give you a detailed introduction to make and its description file makefile.
The most important and basic function of make tools is to describe the interrelationships between source programs through makefile files and to automate the maintenance of compilation work. The makefile file needs to be written in a syntax that explains how to compile each source file and connect to build the executable file, and requires that you define dependencies between the source files. The makefile file is a common way for many compilers-including Windows NT compilers-to maintain compilation information, except that in an integrated development environment, users modify makefile files through a friendly interface.
In UNIX systems, it is customary to use Makefile as a makfile file. If you want to use a different file as a makefile, you can specify the makefile file by using the Make command option similar to the following:
$ make-f Makefile.debug
For example, a program named Prog is compiled from three C source files filea.c, FILEB.C and FILEC.C, and the library file LS, which also contains their own header files A.h, B.h, and c.h. Typically, the C compiler will output three target files filea.o, FILEB.O, and FILEC.O. Suppose FILEA.C and FILEB.C to declare that a file called defs is used, but filec.c not. That is, in both FILEA.C and FILEB.C, there are statements:
The following document describes the relationships between these files:
#It is a example for describing makefile
PROG:FILEA.O FILEB.O FILEC.O
CC FILEA.O FILEB.O Filec.o-ls-o prog
FILEA.O:FILEA.C a.h defs
FILEB.O:FILEB.C b.h defs
This description document is a simple makefile file.
From the example above, note that the first character is a line for the behavior comment of #. The first non-comment line specifies that the prog is delivered by three target files FILEA.O, FILEB.O, and FILEC.O chains. The third line describes how to create an executable file from a file that prog relies on. The next 4, 6, 8 lines specify three target files, along with the. C and. h files that they rely on and the defs files. The 5, 7, and 9 lines specify how to set goals from the files on which the target depends.
When FILEA.C or A.H files are modified after compilation, the Make tool can automatically recompile FILEA.O, and if the FILEA.C and A.H are not modified between the two compilations, and if TEST.O exists, there is no need to recompile. This dependency is particularly important in the compilation of multiple source files. This dependency definition allows the make tool to avoid many unnecessary compilation efforts. Of course, the use of shell scripts can also achieve the effect of automatic compilation, but the shell script will compile any source files, including which do not need to recompile the source files, and make The tool automatically determines which source file should be compiled based on the time that the target was last compiled and the update time of the source file on which the target depends.
The makefile file as a description document generally needs to include the following:
Interdependence between source files
Commands that can be executed
Makefile allows you to use simple macros to refer to source files and their associated compilation information, which is also called macros as variables in Linux. When referencing a macro, you only need to add the $ symbol before the variable, but it is worth noting that if the variable name is longer than one character, it must be added with parentheses ().
All of the following are valid macro references:
The last two references are exactly the same.
Note that some of the predefined variables of the macros, in the UNIX system, $*, $@, $, and $< the values of the four special macros change during the execution of the command, and more predefined variables are defined in GNU make. With regard to the details of predefined variables, the use of macro definitions allows us to break away from those tedious compilation options, making it much easier to write makefile files.
# DEFINE A macro for the object files
objects= FILEA.O FILEB.O FILEC.O
# DEFINE a macro for the library file
# Use macros rewrite makefile
Prog: $ (OBJECTS)
CC $ (OBJECTS) $ (libes)-O prog
If you execute the make command without parameters, you will connect three target files and the library file ls, but if you have a new macro definition after the Make command:
The macro definition that follows the command line overrides the macro definition in the makefile file. If LL is also a library file, the make command will connect three target files and two library files LS and LL.
There is no explicit definition of constant NULL in UNIX systems, so we use the following macro definition when we want to define a null string:
Not only do macro definitions appear after the make command, but you can also follow other command-line arguments that specify the target files that need to be compiled. Its standard form is:
The middle part of the bracket indicates an option. Targets and dependents can contain characters, numbers, periods, and "/" symbols. In addition to references, commands cannot contain "#", nor does it allow wrapping.
In the usual case, the command-line argument contains only one ":" where the command sequence is usually related to the description row of the dependencies between some of the definition files in the makefile file. If the related command sequence is specified for those description lines associated with the target, the associated command commands are executed, even if the Aommand field after the semicolon and (tab) is possibly null. If the row associated with the target does not specify command, the system default target file generation rule is invoked.
If the command line argument contains two colons "::", then the command sequence may be related to all the rows in makefile that describe the file dependencies. The related commands that are pointed to by the description line associated with the target are executed at this time. The build-in rule is also executed.
If you return an error signal other than "0" when you execute the command command, such as an incorrect target file name in the makefile file or a command string that starts with a hyphen, the make operation generally terminates, but if make has a "I" parameter, Then make ignores this type of error signal.
Make can have four parameters: a flag, a macro definition, a description file name, and a destination file name. Its standard form is:
make [flags] [macro definitions] [targets]
The flag bit flags option in the UNIX system and its meaning is:
-F file specifies that the file file is a profile, and if the file argument is "-", then the description file points to standard input. If there is no "-f" argument, the system will default to the current directory named makefile or file named makefile as the description file. In Linux, the GNU make tool searches for makefile files in the current working directory in the order of Gnumakefile, Makefile, and makefile.
-I ignores error messages returned by command execution.
-s silent mode, do not output the corresponding command-line information before execution.
-R prohibits the use of build-in rules.
-N is not in execution mode, outputting all execution commands, but not executing.
-t updates the destination file.
The-Q-Make operation returns status information for "0" or not "0" based on whether the target file has been updated.
-p outputs all macro definitions and target file descriptions.
-D debug mode, which outputs detailed information about the file and the detection time.
The common options for the Linux make flag bit are slightly different from the Unix system, and we only list the different parts:
-C dir Changes to the specified directory dir before reading the makefile.
-I uses this option to specify the search directory when it contains other makefile files.
-H Help Text to display all make options.
-W Displays the working directory before and after the makefile is processed.
Target in a command-line parameter specifies the goal to compile for make, and allows simultaneous definition of multiple targets, in which the target file specified in the target option is compiled in Left-to-right order. If a target is not specified on the command line, the system default target points to the first destination file in the description file.
In general, a clean target is also defined in makefile that can be used to purge intermediate files during compilation, for example:
When you run make clean, the rm-f *.o command is executed, which eventually deletes all intermediate files that are generated during the compilation process.
There are built-in or implied rules in the make tool that define how to establish a specific type of target from a different dependent file. UNIX systems typically support an implied rule based on the file name extension, which is the filename suffix. This suffix rule defines how to convert a file with a specific filename suffix (for example,. c files) to a file with another filename suffix (for example,. o files):
$ (CC) $ (cflags) $ (cppflags)-c-o $@ $<
The default common file name extensions in the system and their meanings are:
. O Target File
. c C Source files
. f Fortran Source files
. s Assembly source files
. y yacc-c Source syntax
. l Lex Source Grammar
Yacc-c source syntax and Lex source syntax are also supported in earlier UNIX system systems. During the compilation process, the system first looks for the target file in the makefile file. c file, if there is a dependency on it. Y and. l files, it is first converted to a. c file and then compiled to produce the corresponding. o file, and if there are no. c files associated with the target and only the associated. y file, the. y file is compiled directly.
GNU make, in addition to supporting suffix rules, supports another type of implicit rule-pattern rule. This rule is more general because pattern rules can be used to define more complex dependency rules. Pattern rules look very similar to regular rules, but have one more% in front of the target name and can be used to define the relationship between the target and dependent files, for example, the following pattern rule defines how to convert any file.c file to a FILE.O file:
A more comprehensive example is given below to further explain the execution of the makefile file and make command, where the make command involves not only the C source file but also the YACC syntax. This example is selected from the "Unix Programmer ' s Manual 7th Edition, Volume 2A" Page 283-284
The following are the details of the description file:
#Description the file for the make command
#Send to print
p=und-3 | Opr-r2
#The source files that are needed by object files
files= Makefile version.c defs main.c donamc.c misc.c file.c \
DOSYS.C gram.y lex.c GCOS.C
#The definitions of object files
objects= vesion.o main.o donamc.o misc.o file.o dosys.o GRAM.O
Make: $ (OBJECTS)
CC $ (cflags) $ (OBJECTS) $ (libes)-O make
$ (OBJECTS): defs
-RM *.O GRAM.C
CP Make/usr/bin/make; RM make
#print recently changed files
Print: $ (FILES)
PR $? | $P
MAKE-DP | Grep-v Time>1zap
/USR/BIN/MAKE-DP | Grep-v Time>2zap
Diff 1zap 2zap
RM 1zap 2zap
LINT:DOSYS.C donamc.c file.c main.c misc.c version.c
$ (LINT) dosys.c donamc.c file.c main.c misc.c version.c \
Ar uv/sys/source/s2/make.a $ (FILES)
Usually in the description file, you should define the command that the output will execute as described above. After the make command has been executed, the output results are:
The final digital information is the output that executes the @size make command. The only output that does not have a corresponding command line is because the @size make command starts with "@", which prevents the printout of the command line on which it resides.
The last few command lines in the description file are useful for maintaining compilation information. Where the Print command line works is the printout of all changed file names after the last make Print command was executed. The system uses a 0-byte file named Print to determine when the print command was executed, and the macro $? points to the file name of the file that was modified after the print file was changed. If you want to specify that the output is sent to a specified file after you execute the Print command, you can modify the macro definition of P:
Make print "p= cat>zap"
Most software in Linux provides the source code, rather than the ready-made executable file, which requires the user to configure and compile the source program according to the actual situation of their own system and their own needs, so that the software can be used. Only by mastering make tools can we really enjoy the free software world of Linux to bring us endless fun.
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