LPC43XX Sgpio I²C Implementation

I²C Sgpio Configuration

Sgpio is a hardware feature of LPC4300 series.

There is sgpio pins called from Sgpio 0 to Sgpio 15.

Sgpio is one of the functions of LPC 4300 pins which can chosen.

Sgpio could work as standard GPIO pins, or do stream processing.

So it provides a number of possibilities for interface implementation.

Each pin of Sgpio have a configuration as shown in Figure 1-7.

The PIN function has a been chosen by SCU (System Control Unit) as Sgpio function.

What the left should was configured with Sgpio pin are set by bits of Out_mux_cfg Register.

OUT_MUX_CFG consists of the parts, P_out_cfg and p_oe_cfg.

P_out_cfg decides whether a slice or gpio_reg generates the output signal (dout).

P_OE_CFG selects whether slice or Gpio_oereg to be output enable (DOE).

All the relevant Sgpio registers information are in appendix B.

Slice is a enhanced feature of Sgpio to accelerate serial streaming.

The construction of one slice is in Figure 1-8.

REG Register is a shift register to generate output or get input for one slice.

Reg_ss is the slice data Shadow register.

POS Register is a down counter.

The first 8 bits (pos_counter) of POS Register indicates the current number of shifts left before the exchange is Tween REG and REG_SS.

The last 8 bits (pos_preset) of POS register sets the reload value of Pos_counter.

REG and reg_ss would exchange the content when the counter pos_counter reaches 0x0.

This feature can is used to change new output value of on slice.

PRESET Register sets the reload value of the counter, in other words, it controls the rate of shift clock.

COUNT Register reflects the slice clock counter value.

When COUNT equals 0x0, pos_counter counts down, and REG shifts once.

All the details about setting of one slice is in section 5.4.

To configure LPC4350 pins to be i²c signal pins, both sgpio pins should be chosen first.

In this demo, Sgpio 1 and Sgpio is defined as SDA and SCL respectively.

With looking up the table in section 6.2 (Pin description) of LPC4350 datasheet (6),

The available pins to is Sgpio 1 and Sgpio could be found.

Possible pins for Sgpio 1 is p0_1, P9_1, and pf_2.

Possible pins for Sgpio is p1_20, P2_4, P4_8, pc_14, and Pd_9.

The pins in the list above is available to use the real board.

In order to choose the proper pins from them, the schematics of the evaluation board have been consulted.

The requirements to define free pins on the board is as follows,

? It should has a jumper between the pin of LPC4350 and a certain chip or circuit.

? The signal of SDA or SCL would not affect the previous function of the PIN.

According to these requirements, the choices left for Sgpio 1 is p0_1, P9_1, and pf_2.

For Sgpio, the pins meet the requirements is p1_20, P2_4, P4_8.

Finally, P9_1 and p1_20 are picked. The overall information of selected LPC4350 pins is in Table 1-1.

Table 1-1: i²c function and sgpio number of selected LPC4350 pins

The System Control Unit (SCU)/IO configuration should is set for each pin.

The PIN configuration registers bit description is in page 227 of LPC4350 User manual, which was also in Appendix C Table C -1.

What should is set in PIN configuration register is

Pin function, pull-up enable, pull-down Enable, slew rate, input buffer enable and input glitch filter.

As for pin function, both of p9_1 and p1_20 work in Sgpio mode numbered as function 6.

For I²c Standard-mode, the signal rates is below MHz, so the pins should is set as slow rate and input glitch filter E Nable.

The pins is set as pull-up enable due to the construction of the I²c Masters and slaves (see next paragraph).

Input buffer is the enabled to make Sgpio streaming possible.

As to create a suitable sgpio configuration for I²c protocol, first should look into the construction
Both master side and slave side (see Figure 1-10).

The SDA line was originally high and the pull up, so Sgpio could does always drive it high.

An example can explain this in figure 1-9.

If Master 2 is always driving SDA line, assume the voltage on Master 2 are 5 V and Master 1 now wants to transfer data and Drive SDA Line Low.

In this situation, the final voltage on SDA line is 2.5V. In conclusion, what should was done was to drive SDA low when there ' s a need.

The condition is exactly the same for SCL line.

The setting of Sgpio pin configuration is in Figure 1-11.

For Sgpio 1, the SDA line, GPIO mode was to generate output, and output value are set by Gpio_outreg register.
Slice M is output enable as a driver.
Slice M is in a self-loop.

Slice I gets the input from Sgpio 1 during i²c data receiving.

The Choose Slice I as input is according to Table 1-5 in section 5.4.

In terms of Sgpio, GPIO mode was to generate output.

Slice K is self-looped and set to be output enable.

Slice D is the clock source for Slice I, M, and K.

To find the "the" to "select clock source for each slice," refer to Table 1-5 in section 5.4.

The selection of slices that was related to output mode was according to the table 1-2 and table 1-3.

The blue blocks represent slices mapping of sgpio 1.

The green blocks indicate slices mapping of sgpio 13.

The output mode and output enable is set by the register called Out_mux_cfg as shown in Table 1-4.

In this demo, the value of a bit 1 in Gpio_outreg are set to BES always 0 in i²c implementation.

So, during i²c data sending,

The output of Sgpio 1 is 1 when slice M generates 0.

The output of Sgpio 1 is 0 when slice M generates 1.

The method above is applied to Sgpio.

In the This is the Sgpio could work well with i²c Slave/master hardware construction (refer to Figure 1-10).

I²c Slice Configuration

Sgpio 1, the SDA signal pin, needs to get the state of buttons by receiving data.

So, one slice should is chosen to get the external data input from Sgpio 1.

According to Table 1-5 (see blue blocks), it's Slice I that's mapped as input to Sgpio 1.

As to get external data pin input for Slice I, set 0 in concat_enable bit in Sgpio_mux_cfg Register (refer to Table 1-6).

Table 1-5: Slices selection for Input or clock source (sgpio_mux_cfg register)

Another important part to configure slices are the shift rate setting.

In order to keep all the slices work at the same shift rate, 4 registers (sgpio_mux_cfg, PRESET, COUNT, and POS) should be Set

• ? Sgpio_mux_cfg:
  Slice I, M, K is set to use slice D as their clock source. (Refer to Orange blocks in Table 1-5)
• ? Preset:controls the shift clock frequency by formula below.
  So set same value to slice I, M, D, K.
  Frequencyshift_clock = Frequencysgpio_clock/(preset+1)
• ? Count:controls the phase of shift clock. Set 0 to Slice I, M, D, K in this situation.
• ? Pos:contains Pos_counter and Pos_preset.
  In this demo, slice Exchange content between REG and reg_ss every.
  So values in Pos_counter and pos_preset should is 32-1 = 0x1F.

I²c programming

A Basic I²c Write transfer consists of

A START condition, followed by 7 address bits,

A one to indicate that it's a write, an ACK (send by the slave),

8 Data bits and another ACK, finalized with a stop condition.

The transfer is a upfront fixed sequence as it depends on the conditions.

One is, the acknowledge responses from the slave is.

The many bytes of data would be sent.

Due to this, it makes sense-to-split the pattern to make it possible-respond to the feedback from the slave.

It ' s also easier to perform a read transfer by separating protocol format into parts.

The I²C protocol is such that it's possible to stall the transfer.

The Sgpio is a using-to-bit registers.

So, the implementation is simpler if the transfer are split into parts which fit in the + bit words.

This approach results in 8 parts:

Start, send data, receive ack/nack, repeated Start, receive Data, send ACK, send NACK, and Stop.

These eight parts could group into several different combinations.

Three typical combinations is as follows:

• 1. Write to Slave:
  Start, send slave address (/w), Receive ACK, send data, send NACK, Stop
• 2. Read from Slave:
  Start, send slave address (R), receive ACK, receive data, send NACK, Stop
• 3. Write and read:
  Start, send slave address (/w), receive ACK, send data, receive ACK,
  Repeated Start, send slave address (R), receive ACK, receive Data, send NACK, Stop (see Figure 1-14).

The data transmission is programmed to be a function named I2c_transferdata.

Eight parts mentioned above is programmed as Eight functions and could is called in function I2c_transferdata.

The aim of function i2c_transferdata is to combine all possibilities of transfer formats.

It can choose whether to read or write and when.

Moreover, the function can react to acknowledge signal sent by slave.

It ' s also possible to judge the validity of data sent by slave and response to it.

The input of i2c_transferdata function is a structure which contains

Slave address, data length (means how many bytes of data) to send or receive, value of the data to send or receive, counter of Transferred bytes.

The data received is transferred-structure as well.

The output of the function is state of transmission, error or success.

Below is the flow charts of the I2c_transferdata function.

The gray Block (Receive) in the ' left ' chart points to the gray block (Start Receive) in the right chart.

The Stop Receive block in the the "right points" of the chart on the left.

The function has a Start and Stop at the beginning and the end respectively, and in between is data streaming.

Followed by START condition, it's the decision whether to send data or not.

If sending data is needed, it starts to send 7-bit slave address with 8th bit low (/w), and then send data.

followed by every byte sent, there is acknowledge receiving and judging if all the data has been sent.

The transmission could stop and send error information if the received acknowledge bit is high (NACK).

If there ' s no need to send any data, or all data bytes has been sent successfully, the code would go to next decision.

This decision was to decide whether to read or not.

If reading is required, the routine would go to the flow chart in the right,

and decide whether to send a repeated START condition or not.

If the transmission have sent data before receiving, a repeated START condition is needed. < Write and Read >

Otherwise, the data transfer directly goes to address sending part.

Next, it sends 7-bit slave address with 8th bit high (R), receives 8-bit data, and checks the data validity to decide to s End ACK or NACK.

If data is not stable on SDA when SCL is high, the transmission would generate a NACK and STOP condition.

Error information is returned as well.

After receiving every data byte and sending ACK, the code would check if it reaches the amount of byte desired to receive.

If The decision is no data to receive, or all data bytes has been received successfully, the transmission would end with a STOP condition.

An important point to notice is, the last acknowledge bit sent before STOP condition should be NACK.

Otherwise, the slave would not recognize it's the STOP condition to come.

Due to the 32-bit shift register and 8-bit data format,

Extending 8-bit data into a used in the Send data part,

and shortening-bits into 8 bits are used in Receive Data.

In this project, there is boards used.

At the beginning of the project, a old board is used, which contains the touch buttons, LED, and PCA9502 as the slave.

The new board is delivered later has push buttons, LED, joystick and PCA9673PW.

PCA9502 is an 8-bit I/O expander with I2c-bus or SPI interface.

It requires writing a register address of PCA9502 before read or write data.

Therefore, some sequences with using the old board contain read and write transfer, and appear .

Since the working, the new chip in the new board was different, data transmissions is either a read transfer or a WRI Te transfer.

So, not all the eight parts is actually working in the latest demo.

The structure of six functions above is very similar.

The basic idea was to change the values in Regi (i:represents the slice number)

and Reg_ssi of output enable slices to generate different patterns.

Changing the values at the right time is the main difficulty.

For example, if a new value was written into Regi without any condition, the former pattern was changed to new one before it Totally shifts out.

In a result, the pattern generated in this-is-mixed with the previous value and the new value.

So a feature of Sgpio are used in this case.

The shift register REGI can shift out of the bits and stop after exchanging with Reg_ssi.

In other words, Posi could countdown once in one cycle of the if it is desired.

Detail steps is included in the example with Slice A (0) below.

ctrl_enabled = 0 (clear enable of all slices)
ctrl_disabled = 0 (Clear disable of all slices)
Reg[0] = 0xffff0000 (give a initial value of output)
ctrl_enabled = 1 (Enable slice A which is now shifting sixteen 0s and sixteen 1s)
ctrl_disabled = 1 (slice A would shift one more old pattern and stop)
Wait (until Pos_counter reloads its value)
Reg[0] = 0xFFFFFFFF (change a new value to output)
ctrl_disabled = 0; (Slice A generates all high continually as new pattern)

In terms of "right" to "change value", the delay part above is made of the "a" and "Loops in the" demo, here is one example F or slice K:

while (lpc_sgpio->pos[10]==0x1f1f);
while (lpc_sgpio->pos[10]!=0x1f1f);

The second while-loop is to wait for until POS reloads its value.

The reason to has the first while-loop is and in the program, the delay sections (while loop) is often used.

When POS equals 0x1f1f and it costs some time counting down to 0x1f1e, 0x1f1d and so on.

The code would run very fast and skip some while loops if there ' s is only the second while.

So the first and is to avoid skipping steps in transmission.

Another important thing is this value in while-loop condition should be 0x1f1f rather than 0x0.

It ' s because the shifting disabled function is designed to pause the sequence at the moment POS have reloaded the new value .

The flow chart of Start function is in Figure 1-16.

For Send data, receive ack/nack, repeated Start, receive Data, send ACK, send NACK, and Stop, only one thing should is Cha Nged.

That's the desired value to being written in REG and reg_ss of slice K and slice M.

As shown in the figure, it's a complete read transfer.

The master first generates START condition, sends slave address with 8th bit high,

And then keep SDA high in 9th clock to wait for the slave to send the acknowledge bit.

At this time the slave keeps driving SDA line low during 9th clock, it means the slave have received the address.

The master receives data in the next 8 clocks and then sends an ACK signal.

During Next 8 clocks, the master receives another byte of data.

Then it's the master ' s responsibility to send NACK to stop.

The master keeps SDA high to inform the slave to stop.

The whole transmission is terminated by a STOP condition.

Conclusion

I²C protocol could be implemented to SGPIO interface by software programming.

The demo proves it's possible for sgpio to work in rule of communication protocols.

Error detecting is also realizable.

There is still some problems left to being improved with I²C protocol:

• 1. The output of function i2c_transferdata is ERROR or SUCCESS.
  It can be detected if there are any error during executing i2c_transferdata.
  However, the conditions could leads to the error state.
  One is receiving NACK from slave when it sends address or data.
  The other are the data received from slave couldn ' t meet data validity.
  When the routine get a error state of i2c_transferdata, it couldn ' t define which part of the transfer generates error.
  So it's better to has overall information about where and what's the error is.
• 2. The wait part in Figure 1-16 was made of a while loop.
  To wait until the exact moment, It's better to has a smarter and safer solution instead of while loops.
• 3. Now the code was working on ARM M4 Core. The desired core to deal and peripherals is ARM M0.
• 4. Between M4/m0 core and Sgpio, there is a bridge.
  The data stream should get over the bridge to reach Sgpio.
  So it might cause latency if the sequence is complex and long.
  A test of Long data transmission is recommended to see the performance.
• 5. I²c protocol contains Standard-mode, Fast-mode, Fast-mode Plus, and the high-speed mode.
  The protocol achieved is under Standard-mode. realize other modes.

LPC43XX Sgpio I²C Implementation