Operating system memory management

Physical memory

To effectively use the physical memory on the machine, Linux divides the memory into several functional areas during system initialization:

<喎?http: www.bkjia.com kf ware vc " target="_blank" class="keylink"> VcD4KPHA + PGJyPgo8L3A + examples/27P9z9S/examples + samples/b7d0OjSqtC0tb2/examples + examples/L2bu6s + XH + samples/6 cnosb.pdf + records + xNq05rXE1 + 6687 K/t9bKx7/JuanL + records/6 czhs/records + t9a2zs + 1zbM8L3U + records + 1zbPKx7/records + records /examples + cve-vcd4kpha + PGJyPgo8L3A + examples/examples + PGJyPgo8L3A + examples + samples + z9/examples + zu/samples + PGJyPgo8L3A + example + 08 examples + signature + signature/Signature/A7cTatOa12Na3yc + signature/Signature + 1rK/tdjWt7/Signature + CjxwPqG + signature + IDwvcD4KPHA + signature/Signature + Signature = = "http://www.2cto.com/uploadfile/Collfiles/20140425/20140425090834379.jpg" alt = "\">

That is, programmers (both compiled and advanced languages) can regard the memory distribution as shown in. They can think that the memory only has their own programs and they own the CPU exclusively.

This is a simple abstraction provided by hardware and the operating system to programmers.

(Underlying implementation: address translation and task switching are transparent to programmers)

Logical AddressIt refers to the segments produced by the program.What is the offset address? Http://www.bkjia.com/kf/yidong/wp/ "target =" _ blank "class =" keylink "> memory/memory + oaM8L3A + Memory + memory/rWxrbUy/vatmu1zeriq1_w/memory + Memory + memory/W1Nq1xLLZ1/fPtc2zuPi9 + examples/examples + examples/examples + oaM8L3A + examples + sLru + Gy + sn6wt + examples/samples/g06a2zrXEu/m12Na3vs3J + rp1_cvsu7j2z9/examples + examples/ release/rWxqOsxMfDtM/release/Q1LXY1re/release + CjxwPiA8L3A + release/tdjWt9fcz9/release + release/rWxjwvaDE + release/release + release = "http://www.2cto.com/uploadfile/Collfiles/20140425/20140425090834380.jpg" alt = "\">

In protection modeThe segment register does not store the base address of the addressing segment, but a descriptor in a segment descriptor tableIndex value in the table. The segment descriptor specified by the index value contains the base address of the memory segment to be addressed, the segment length value, and the segment access privilege level. (In this way, the information in the access segment through the segment descriptor can be checked for security, which is the so-called protection mode)

In this way, addressing a memory address in the protection mode requires one more step than in the real mode.Segment descriptor table.

Note: If you do not define a memory linear address space area in a segment descriptor, the address area cannot be addressable at all, and the CPU will reject access to the address area.

There are three types of Descriptor tables for storing descriptor items, each of which is used for different purposes.

IDTInterrupt Descriptor Table, which stores segment descriptors that define Interrupt or exception handling processes.The IDT table directly replaces the interrupt vector table in the 8086 system.. (This allows you to perform permission checks when you jump to an interrupted program .)

GDTGlobal Descriptor Table, which can be referenced by all programs to access a memory segment.

LDTA Local Descriptor Table usually uses an LDT Table for each task. Each LDT table provides more available descriptor items for the corresponding task, becauseProvides a range of addressable memory space for each task.

These tables can be stored anywhere in the linear address space. To enable the CPU to locate the GDT table, IDT table, and current LDT table, you need to set the CPU separately.GDTR,IDTRAndLDTRThree special registers.

It can be seen that the Local Descriptor Table LDT of each task is also a memory segment defined by the descriptor in GDT. The LDT segment contains the code segment and data segment descriptor of the corresponding task, so the LDT segment is very short. Similarly,The task status segment TSS of each task is also a memory segment defined by the descriptor in GDT. (TSS is used to automatically save the CPU or restore the current execution context of related tasks during Task Switching)

Memory paging Management

The basic principle of the memory paging management mechanism is to divide the entire CPU linear address memory area into a memory page with a page size of 4 kb. When the program applies for memory usage, the system allocates memory pages.

To use the paging mechanism in X protection mode,The highest position of the control register CR0 needs to be.

The system's CPU can provide up to 4 GB linear address space.

Memory Management of the Operating System (for reference only)

There are two methods for memory management:

I. Linux 0.12 kernel as an example (Click me) II. Linux 2.x kernel as an example (Click me)