(Original) how to use the system to build a Linux system that can run μC/OS-II on de2 )? (SOC) (Quartus II)

Abstract
I have discussed this subject before, but now it seems that some design projects are still being modified, so I plan to rewrite it.

Introduction
Environment: US us II 7.2 SP3 + niosii eds 7.2 SP3 + de2 (Cyclone II ep2c35f627c6)

In the (original) how to build a self-built systems with the system can run μC/OS-II on de2 niosii? (IC design) (de2) (Quartus II, according to fjl, it was found that the initial design was feasible, but there were still some shortcomings:
1. It is clear that only SRAM is used, and tristate bridge and CFI Flash are added to the memory.
2. Due to limited skill at the time, some solutions are incomplete.

Therefore, we decided to recreate a more refined niosii. If you are a beginner of the niosii and systems System system builder, we suggest that you follow) how can I build a system for running μC/OS-II on de2 with the help of the system? (IC design) (de2) (Quartus II, this article describes how this document is different from the previous article.

Step 1:
Add the required IP Address

And (original) how to build a system that can run μC/OS-II on de2 with the help of the system? (IC design) (de2) (Quartus II, therefore, you only need to add the SRAM and tristate bridge and CFI Flash are not required.

As a result, only the MHz clock is used for the niosii, and the 50 MHz clock is not required.

Step 2:
Set the Reset vector and exception vector of the niosii CPU

Since only SRAM is available now, the Reset vector and the exception vector are all set in SRAM.

Step 3:
More refined top Module

De2_nios_lite.v/OpenGL

1 /*  
2 (C) oomusou 2008 Http://oomusou.cnblogs.com
3
4 Filename: de2_nios_lite.v
5 Compiler: Quartus II 7.2 SP3 + Modelsim-Altera 6.1g
6 Description: de2_nios Lite version for SRAM only
7 Release: 08/29/2008 1.0
8 */
9 Module De2_nios_lite (
10 Input Clock_50, // On board 50 MHz
11 Input [ 3 : 0 ] Key, // Pushbutton [3: 0]
12 Inout [ 15 : 0 ] Sram_dq, // SRAM Data Bus 16 bits
13 Output [ 17 : 0 ] Sram_addr, // SRAM Address Bus 18 bits
14 Output Sram_ub_n, // SRAM low-byte data mask
15 Output Sram_lb_n, // SRAM high-byte data mask
16 Output Sram_we_n, // SRAM write enable
17 Output Sram_ce_n, // SRAM chip enable
18 Output Sram_oe_n // SRAM output enable
19 );
20
21 Wire Cpu_clk;
22 Wire Cpu_reset;
23
24 Reset_delay U0 (
25 . IRST (Key [ 0 ]),
26 . Iclk (clock_50 ),
27 . Oreset (cpu_reset)
28 );
29
30 Sdram_pll U1 (
31 . Inclk0 (clock_50 ),
32 . C1 (cpu_clk)
33 );
34
35 Nios_ii u2 (
36 . CLK (cpu_clk ),
37 . Reset_n (cpu_reset ),
38 // SRAM
39 . Sram_addr_from_the_sram (sram_addr ),
40 . Sram_ce_n_from_the_sram (sram_ce_n ),
41 . Sram_dq_to_and_from_the_sram (sram_dq ),
42 . Sram_lb_n_from_the_sram (sram_lb_n ),
43 . Sram_oe_n_from_the_sram (sram_oe_n ),
44 . Sram_ub_n_from_the_sram (sram_ub_n ),
45 . Sram_we_n_from_the_sram (sram_we_n)
46 );
47
48 Endmodule

Step 4:
The Hello world and hello microc/OS-II project templates of the line of niosii eds can be used.

Download the complete program
De2_nios_lite_sram.7z

Conclusion
If you think that you have built your own system for the nio ii system, you can use the (original version) de2_nios_lite 1.0 (SOC) (nano II) (Systems builder) (de2) and (formerly known) de2_nios_lite 1.1 (SOC) (nano II) (Systems builder) (μ c/OS-II) (de2), which is a simplified version of the nano II, or you can test the reference design of de2 CD.

See also
(Original) how to build a system on de2 run μC/OS-II with the system? (IC design) (de2) (Quartus II)
(Original release) de2_nios_lite 1.0 (SOC)
(Formerly known) de2_nios_lite 1.1 (SOC) (nano II) (Systems builder) (μC/OS-II) (de2)