PCIE_DMA Example two: EDK simulation of xapp1052

A: Preface

This blog is written by a friend of mine, who wants to learn the design of the PCIe DMA controller based on the FPGA, but there is no suitable xilinx development Board on hand, and xapp1052 does not provide the simulation code to make his learning difficult. So I think, or use EDK to build a small system, and then use Modelsim to simulate the xapp1052 DMA transceiver control, this should be the most comprehensive understanding of PCIE_DMA, I hope everyone will be helpful.

Second: Pre-preparation

1, Xapp1052 Demo (http://download.csdn.net/download/yuzeren48/7723795)

2. ISE14.1 Kit

3, Basic will use EDK (mainly Xilinx Platform studio,xps and software development KIT,SDK)

Three: Operation steps

1. Compile the library file, copy and paste the selected parts of D:\Xilinx\14.1\ISE_DS\ISE\verilog\mti_se\10.1b\nt\modelsim.ini to D:\modeltech_10.1b\ In Modelsim.ini

2. Open XPS, create a new minimum system, use the Microblaze and PLB bus, the bus mount hardware IP2 shown, the hardware bus address 3 is shown.

Figure 2 Hardware IP

Figure 3 Hardware IP bus address

3, after the completion of the hardware system, export to the SDK

4. After opening the SDK, create a new BSP package, please refer to "Xilinx FPGA development Practical Tutorial"

Then create an empty Xilinx C Project, named example.

Find ioctrl.h under E:\xapp1052\dma_performance_demo\win32_sw\win32_driver\source, copy and paste to E:\pcie_edk\EDK\workspace\ Example\src

Add the C file in Src, named rc_example.c. Then the

D:\Xilinx\14.1\ISE_DS\EDK\sw\XilinxProcessorIPLib\drivers\pcie_v4_01_a\examples\xpcie_rc_enumerate_ The code in EXAMPLE.C is copied to rc_example.c

Make the following changes to RC_EXAMPLE.C:

#define PCIE_CFG_BAR_0_ADDR         0x11110000#define pcie_ep_cfg_bar_0_addr       0x0000ffff        //Remote EP bar0# Define PCIE_RC_CFG_BAR_0_ADDR      0x0000eeee         //RC BAR0

Add to:

//-------------------BMD Mrd test* (unsigned int*) (xpar_plbv46_pcie_0_ipifbar_0 + dcr_offset) = Xil_endian      SWAP32 (0x00000001); 1.        DMA assert reset* (unsigned int*) (xpar_plbv46_pcie_0_ipifbar_0 + dcr_offset) = XIL_ENDIANSWAP32 (0x00000000);            * (unsigned int*) (xpar_plbv46_pcie_0_ipifbar_0 + read_addr_offset) = pcie_rc_cfg_bar_0_addr; 2. Read DMA TLP Address register* (unsigned int*) (xpar_plbv46_pcie_0_ipifbar_0 + read_size_offset) = Xil_endianswap32 (0x     0000050/4); 3. Read DMA TLP Size register* (unsigned int*) (xpar_plbv46_pcie_0_ipifbar_0 + read_count_offset) = XIL_ENDIANSWAP32 (0x000      00100); 4. Read DMA TLP Count register* (unsigned int*) (xpar_plbv46_pcie_0_ipifbar_0 + read_pattern_offset) = XIL_ENDIANSWAP32 (0xA3      A2A1A0); 5. Read DMA Data Pattern register* (unsigned int*) (xpar_plbv46_pcie_0_ipifbar_0 + dcsr_offset) = XIL_ENDIANSWAP32 (0      x00010000); 7. MWr Start 

Or

//-------------------BMD Mrd test* (unsigned int*) (xpar_plbv46_pcie_0_ipifbar_0 + dcr_offset) = Xil_endian      SWAP32 (0x00000001); 1.        DMA assert reset* (unsigned int*) (xpar_plbv46_pcie_0_ipifbar_0 + dcr_offset) = XIL_ENDIANSWAP32 (0x00000000);            * (unsigned int*) (xpar_plbv46_pcie_0_ipifbar_0 + read_addr_offset) = pcie_rc_cfg_bar_0_addr; 2. Read DMA TLP Address register* (unsigned int*) (xpar_plbv46_pcie_0_ipifbar_0 + read_size_offset) = Xil_endianswap32 (0x     0000050/4); 3. Read DMA TLP Size register* (unsigned int*) (xpar_plbv46_pcie_0_ipifbar_0 + read_count_offset) = XIL_ENDIANSWAP32 (0x000      00100); 4. Read DMA TLP Count register* (unsigned int*) (xpar_plbv46_pcie_0_ipifbar_0 + read_pattern_offset) = XIL_ENDIANSWAP32 (0xA3      A2A1A0); 5. Read DMA Data Pattern register* (unsigned int*) (xpar_plbv46_pcie_0_ipifbar_0 + dcsr_offset) = XIL_ENDIANSWAP32 (0      x00010000); 7. MWr Start 

When initializing the RC side configuration register, add the code:

----------------------------------------------------Configure rc//write Address to PCIe bar0headerdata = pcie_rc_ CFG_BAR_0_ADDR; Xpcie_writelocalconfigspace (Xlnxrootcomplexptr, Pcie_cfg_bar_0_reg, Headerdata);

The RC end pcie_bar0 is set to 0x0000eeee (with a size end, so the actual address is 0xeeee0000).

The enumeration makes it necessary to initialize the remote EP, modify the code, enable the master enable bit:

ConfigData |= (pcie_cfg_cmd_busm_en | Pcie_cfg_cmd_mem_en | 0x80000000    

Modify the EP End pcie_bar0 to 0x0000FFFF (with the size end, so the actual address is 0xffff0000):

/* Write Address to PCIe BAR0 */configdata = (pcie_ep_cfg_bar_0_addr | Pciebusnum | Pciedevnum | Pciefunnum);

Finally, all printf functions are removed, printing is too slow to affect the simulation.

Build the Elf file after compiling, open XPS, set SIM executable:

Set preference in edit

Then click Generate HDL Files, and then launch Simulator

In the open Modelsim script bar, enter C;

Complete RC compile, and then enter S; Start the simulation of the RC end.

5. To simulate the entire PCIe DMA, you need to modify the. \edk\simulation\behavioral folder under the SYSTEM_TB.V, add the EP end user logic in SYSTEM_TB.V, modify the following:

START USER CODE (do not remove the line)//User:put your stimulus here. Code in this//section is not being overwritten.      Initial begin pcie_sysclk_p = 1 ' B1;   Forever # (Fpga_0_clk_1_sys_clk_p_pin_period) pcie_sysclk_p = ~pcie_sysclk_p;      100MHz End Initial Begin pcie_sysclk_n = 1 ' b0;   Forever # (Fpga_0_clk_1_sys_clk_p_pin_period) pcie_sysclk_n = ~pcie_sysclk_n;  100MHz Endreg Ep_pcie_sysclk_p;reg ep_pcie_sysclk_n;      Initial begin ep_pcie_sysclk_p = 1 ' B1;   Forever # (4000) ep_pcie_sysclk_p = ~ep_pcie_sysclk_p;      -MHz End Initial begin ep_pcie_sysclk_n = 1 ' b0;   Forever # (4000) ep_pcie_sysclk_n = ~ep_pcie_sysclk_n;    MHz Endwire Ep_pci_exp_txp;wire Ep_pci_exp_txn;        [email protected]* begin plbv46_pcie_0_rxp_pin = EP_PCI_EXP_TXP;     Plbv46_pcie_0_rxn_pin = EP_PCI_EXP_TXN; ENDXILINX_PCIE_2_0_EP_V6 # (. Pl_fast_train ("TRUE")) EP (//SYS Inteface     . Sys_clk_p (Ep_pcie_sysclk_p),. Sys_clk_n (Ep_pcie_sysclk_n),. Sys_reset (Fpga_0_rst_1_sys_rst_pin), ' ifdef ENA Ble_leds//Misc signals. LED_0 (Led_0),. Led_1 (Led_1),. Led_2 (Led_2), ' endif//pci-express Inter      Face. Pci_exp_txn (EP_PCI_EXP_TXN),. PCI_EXP_TXP (EP_PCI_EXP_TXP),. Pci_exp_rxn (Plbv46_pcie_0_txn_pin),  . PCI_EXP_RXP (Plbv46_pcie_0_txp_pin)); END USER CODE (do don't remove this line)

For simulation convenience, after modifying the SYSTEM_TB.V, create a new Bmd_sim folder under E:\pcie_edk\EDK\simulation, and system_ under the Behavioral folder TB.V Copy to the Bmd_sim folder, write the simulate_mti.do file, writing the EP end file that needs to be compiled (mainly including PCIe hard core and XAPP1052DMA) as the . f file.

Vlog-work work +incdir+e:/pcie_edk/coregen/ep_1_7/v6_pcie_v1_7/example_design         +define+simulation         + Define+pcie2_0         $env (XILINX)/verilog/src/glbl.v-       F. /bmd_sim/ep_v6.fvlog-work work. /bmd_sim/system_tb.v

PCIE_DMA Example two: EDK simulation of xapp1052