"Go" Quartus II call Modelsim seamless emulation

This article is reproduced, write good, recently learning Modelsim simulation, the online tutorial is very messy, I think good finishing paste out, the opportunity to write a detailed point later.

Quartus called in Modelsim the process

1. Set up simulation tools
Assignment è setting è EDA Tool Setting è simulation Choose the tools you need.

2. Automatically generate test incentive file Template:
Processingèstartèstart Test Bench Template writer

After we click the system will automatically be in the directory: current folder è simulation è modelsim ( This folder name is related to the simulation tool you selected to generate a test incentive file Xxx.vt (Verilog test Bench) or XXX.VHT (VHDL test Bench), the file name and the top of your project The name of the module is the suffix. vt or. Vht.

3. Edit walk-around generated test bench file
We add the motivation and initialization statements we need, and here we have to change the module name of test Bench to TB (we'll see that the name is associated with the following settings).

4. Connect test Bench, we need to automatically invoke the simulation tool from Quartus, so we need to set the native link option.

A) or in the Simulation Settings page, set the Native Link dialog box. We're here because we need the tool to invoke the excitation automatically so check

b) Click on the test benches on the right and we need to set up an associated test bench here.

Here is a dialog box that lets you specify test bench, because we didn't specify any test bench before, so this is blank.

c) Specify test bench
Because we are the first to produce test bench, click New.

Clicking New will result in a dialog box for the new test bench setting, where you bind the test bench with your corresponding test bench file.

Here we enter a name of "MY_1ST_TB" in the dialog box of test bench name, and we will see that MY_1ST_TB is also automatically displayed in the top level module in Test Bench dialog box below. Note that this name should be the module name in your test bench, we have changed the module name of test Bench to TB before the 3rd step, so we should change the name of the dialog box to TB.

d) Add test bench file

5. Perform simulation
When these settings are complete, select the menu
Toolèrun EDA Simulation Toolèeda RTL Simulation

You can directly invoke Modelsim for simulation.

6. Tips:
We call the simulation this way, if it is Modelsim AE will not compile Lib file each time, but if we are using the Modelsim se version, each call will need to recompile the library, very uncomfortable, here we recommend to modify the script file, for simulation.

A) When we have finished running the simulation, we stay on the Modelsim interface as we described earlier.

b) on the command line of the Modelsim interface, we point up the arrow keys and we'll see our last instruction, we can
Do xxxx.do This description of the tool to execute the last command xxxx.do this script file, our example here is
Do oversampling_core_run_msim_rtl_verilog.do

I. We know the script that the tool executes, and we can change the script as we think. Use
Edit Oversampling_core_run_msim_rtl_verilog.do command, you can see the contents of this script (of course we can also use Ultra Edit or vim and other text editing software to open this script file). This script is usually divided into 3 parts of the library file compilation section, design file compilation, run parameter setting and start execution part

II. Generally, the library file only needs to be compiled at the time of the first compilation, so we just need to specify the location of the library file at the time of simulation, so we don't need to compile it every time. So we can comment out the library file compilation section. The part of the red box in the following illustration is the compiled part of the library that is commented out, which saves our simulation time, and note that in the scripting language, # is an annotation character.

III. We save the edited script file as Sim.do, and in a later simulation we can run the do sim.do directly in the script in the Modelsim command line (first of all, we need to change the Modelsim working directory to the project folder / simulation/modelsim/).

c) In addition, the waveform file generated by the script is usually added to the top of the test bench in the graphics screen we can see in the 3rd part of the script (run parameters and start execution) section, the default command
Add wave *, this command is to tell the top of test bench all the letters to join the Wave window.

For us, in the commissioning phase, there are a lot of low-level signals are to be observed, so we need to manually modify the command

I. In the Modelsim window, select the module you want to care about, and right-click to add your own signal to the wave waveform

II. In the Wave window we can save the format of this waveform, in the Wave window midpoint menu Fileèsave ... Select the file name wave.do.

III. In the script we execute add wave *, this command is replaced with do wave, you can automatically add the waveform you want to observe each time you perform the simulation.

7. The last question, how to compile a library file once, so that the software will not compile every time. In fact, Altera has prepared the appropriate options for customers, but hidden deep, not easy to find.

A) Compile the library once:

I. Click Toolèlaunch EDA Simulation Library Compiler

II. We will see a page that lets us select the device. Choose the settings below, depending on your situation. Click Start Compile, the software will automatically help you to complete the compilation, and then switch off, you should have completed the compilation of the library.

Iii. Next we need to make some changes in the QII's simulation Settings page.
We need to go back to the setup screen
Assignmentèsettingèsimulationèmore Nativelink Setting

Set the appropriate path.

OK, re-run the simulation, you will find no more compile our library files.

"Go" Quartus II call Modelsim seamless emulation