s3c2440 Linux boot Process Analysis (i)--sc2440 processor architecture

1.1. S3C2440 Processor Architecture

The structure of the s3c2440 processor, as shown, is the core unit of the ARM9TDMI processor core, including the 16K instruction cache and 16K data cache, as well as the separate instruction and data MMU unit. The CP15 is a coprocessor (co-processor). Connect to external devices via the AMBA2.0 (Advanced microcontroller bus Architecture) bus interface.

Figure 1 s3c2440 processor block diagram

IVA refers to the virtual address of instruction, the pseudo-location of the instruction, and DVA refers to the data virtual address. IPA refers to the instruction physical address, the physical location of the instruction, and the DPA refers to the data physical address, which refers to the physical addresses.

The package size of the s3c2440 processor is the 14MMX14MM,289-FBGA package type. The operating frequency is up to 400MHz.

The 2.0 Amba Bus standard defines three sets of buses as shown in the following table:

Table 1 Three sets of buses in Amba bus standard

bus name	full name	description
AHB	The Advan CED high-performance bus High performance bus	is applied to high performance, high clock frequency system modules, which constitute a high performance system backbone bus.
ASB	The advanced System Bus System bus	is the first-generation AMBA system bus, which has a smaller data width than AHB and supports typical data widths of 8-bit, 16-bit, 32-bit.
APB	The advanced Periph eral Bus Peripheral bus	is a local two-level bus that is connected via a bridge and a secondary. It is primarily designed to meet the interconnection of devices that do not require high-performance pipelined interfaces or that do not require a high-bandwidth interface.

The peripherals of the s3c2440 processor are connected to the Amba bus as shown.

Figure 2 s3c2440 external device connection diagram

The MPLL PLL generates clocks that are used by various devices on the AMBA bus. AHB bus, mainly includes LCD controller, LCD DMA module, USB host controller, Extmaster (allow external devices as the master of the bus), NAND controller, NAND flash boot loader, bus controller, arbiter and decoder, Interrupt controller, power management module, camera interface module, memory controller (including SRAM, NOR Flash and SDRAM three kinds).

Various peripherals are mounted on the APB bus, including 3 UART,USB devices, SDI/MMC card, watchdog customizer, bus controller, arbiter and decoder, 2 SPI bus, I²c bus, I2S bus, GPIO interface, RTC Real Time Clock, ADC analog-to-digital converter, Timer/ PWM generator, AC97 audio codec.

1.2. s3c2440 Memory address space

The address space for the s3c2440 is as follows:

Figure 3 Memory mapping after s3c2440 reset

As you can see, the s3c2440 memory controller divides the accessible memory into 8 banks, each bank passes through the ngcs[0~7] pin, takes up space of 128MB, and provides a total of access to 1GB of memory space. The first 6 banks have access to the Srom (including ROM and SRAM), and the latter two banks have access to ROM, SRAM, and SDRAM.

Depending on the om[1:0] pin, you can choose whether to use NAND flash as the boot ROM, where there is a different mapping of the address space. Specifically, the mapping between the Bank0 and the internal 4K startup SRAM (boot Internal SRAM) is different. Boot Internal SRAM is a dedicated SRAM storage area inside the processor, 4K in size, dedicated to system startup.

When the value of om[1:0] is 01 or 10 o'clock, Bank0 can access srom, the internal 4KB startup SRAM is located at 0x4000_0000, when the value of om[1:0] is 00 o'clock, select NAND flash as the boot RAM, Bank0 cannot access srom at this time, The internal 4KB startup SRAM is located at the address of Bank0 0x0000_0000.

When NAND Flash is selected as the boot ROM, the NAND Flash boot loader module automatically reads the first 4K data from the NAND flash to the boot RAM, then resets the command from the startup RAM to start execution.

Figure 4 Bank6 and Bank7 addresses for s3c2440

Bank6 and Bank7 are used to connect SDRAM, whose starting and ending addresses are configurable as shown in. Bank6 address must be starting from 0x3000_0000, according to the SDRAM memory size, BANK6 address end, and then Bank7 directly from the end of the Bank6, so Bank6 and Bank7 form a physically contiguous address space. The specific configuration requires the Banksize dedicated register to be set. As shown in.

The address of the Banksize register is 0x4800_0028, and its bit[2:0] is only a BANK6/7 mapping, indicating the size of the bank's memory space.

The s3c2440 uses an external SDRAM at a frequency of around 133MHz.

The address of the Banksize register is 0x4800_0028, and its bit[2:0] is only a BANK6/7 mapping, indicating the size of the bank's memory space.

The s3c2440 uses an external SDRAM at a frequency of around 133MHz.

1.3. Memory connection of the TQ2440 Development Board

The memory address space of the s3c2440 chip is described in the front, and here we give a practical example through the design of the TQ2440 Development Board. TQ2440 is a development board based on s3c2440 processor which is provided by Guangzhou Tian Inlay Computer Technology Co., Ltd., and its memory connection structure is as follows:

Figure 6 Memory connection of the TQ2440 Development Board

As you can see, the TQ2440 uses only 2 of the 8 memory banks in the s3c2440 processor, namely Bank0 and Bank6. Bank0 Connection 2MB nor Flash, data width of 16BIT;BANK6 connection 2 data width of the SDRAM particles 16bit, each granular memory capacity of 32MB, composed of a total capacity of 64MB data width 32bit of the DDR main memory. With NAND flash controller, the 8bit data width is connected to NAND flash with 256MB capacity.

The relevant configuration of the Nand Flash controller is primarily done via pins, which include:

On TQ2440, om[0] can be selected by the dial switch, om[1] ground. OM[1:0] can only be selected as 00 or 01, 00 means NAND flash boot, 01 is the NGCS0 Bank is 16bit mode. NGCS0 is connected on nor flash, that is, from the 16bit data bus width of NOR flash boot.

The configuration pin of the NAND flash controller on the TQ2440 is connected as follows, the NAND flash model used on the Development Board is k9f2g08u0a, so the NR5 resistor is not welded.

Figure 7 NAND Flash controller configuration for the TQ2440 Development Board

As you can see, the value of the Ncon pin is the pin value of 1,GPG14 for the 1,GPG13 pin is 1,gpg15 pin value of 0. These values correspond to the characteristics of the K9F2G08U0A chip-a memory capacity of 256MB (2Gbit), a Page size of 2KB, 5 address Cyle, and a data width of 8bit.

s3c2440 Linux boot Process Analysis (i)--sc2440 processor architecture