(Simplified) Hardware Design (C/C ++) (c) (c2h) (News)

Abstract
When the size and accessibility of embedded systems increase, the development and integration time is a limiting factor, during design, a large number of components are combined on different chips, resulting in high costs and difficulties, the challenge of integration and ingress/egress management also increases the number of shards on a daily basis. In addition, because of the demand for increased efficiency, the customer usually needs to use the customer's hardware, in order to speed up the previous computation work of using the microprocessor to perform related operations, as a prerequisite.

Introduction
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For embedded system design, FPGA has increasingly become an ideal solution for these challenges. The current generation of components is already large and fast, in addition, it is highly cost-effective. Through rapid prototyping and on-site availability capabilities, it will be able to include many or all of the system components. In addition, many existing development tools will make it easier to quickly develop embedded programmable chip systems.

In this articleArticleMedium, this article will discuss the development of three embedded systems, including cross-hardware system integration, embedded software development, and auto-dynamic hardware acceleration for ANSI/ISO-standard C-language functions. tool. As a system integration tool, the system builder can automatically combine the Intellectual Property Model in the system with the objective model, this product produces high-performance FPGA Architecture interoperability. Niosⅱ is a highly configurable micro-processor. It integrates with IDE (integrated development environment) and supports extensive programming and production systems. The niosⅱ C-to-hardware (c2h) connector is a time-sensitive ansi c language tool for performance acceleration, these programs can also be converted into hardware accelerators in FPGA. The above three tools will be able to work closely together to generate a natural and streaming hardware/software platform development process.

■ System Integration

The c2h compiler can be used in systems integration tools such as the Intel® systems System Builder, which allows the design to be used in the GUI (graphic user interface) the following components are combined with the operator, the recorder, and the operator. The list of components and the Operator moment are displayed, the system builder can generate the HDL of all components in the system ), this is a high-resolution HDL design case that includes the autonomous product interaction and arbitration protocols, it can also be used to automatically create The Modelsim case, master, and test platform ).

The c2h accelerator is a customized, cost-effective, high-performance, high-performance system builder that can be automatically inserted into the system, the accelerator is connected like other system components, and the system is connected using a mutually compatible architecture that can generate production.

■ SYSTEM Interaction

The avron cross-frame structure is used to collect the component assembly to the memory ing component of the memory system, its functions are similar to traditional shared systems, but they use dynamic channels, memory storage devices, and local arbitration devices to Increase the efficiency. Through the combination interface of the aveon master and the integration interface connecting from the local port to the system, the combination of the master from the frame structure that was built by the system builder was completed, integrate the entire system.

Any master or slave port can have a connected zookeeper, And the avron communication architecture can be transparent to the arbitration from the slave port, to synchronize multiple master control management, which inserts an arbitration module in front of each slave port to manage different master ports, and extract the interaction between systems from these modules of the master port. The same practice is also used in the slave port. When 1 indicates that the avron transport architecture is connected to multiple slave and master ports in the system.

The c2h memory generator utilizes the precision functional components of aveon, including address decoding, resource routing, waiting for zookeeper insertion, streamline, dynamic zookeeper streaming, arbitration from multiple synchronous master ports, and regionalization Management the time when the domain spans the chip and the off-chip interface.

■ Niosⅱ micro processor

The niosⅱ micro-processor is a kind of smart processor that can be used. Its configurable and configurable capabilities can meet the cost/efficiency considerations in a wide range, it is a typical Hierarchical Architecture optimized for FPGA, with 32-bit instructions and materials, 32 general-purpose memory storages, three command formats, 82 three computing domain commands, up to 256 customer-driven commands, and Selected hardware multiplier and delimiters. Integrated Development Environment (integrated development environment); IDE) to make development easier.

On the compute system, you can use either of the following methods to increase the efficiency of the computation operations: extends the instruction set of the processor through the objective hardware commands written by using the HDL, and transfers it to the operator of the processor, or, through the creation of a customer-driven hard accelerator model, these two methods are different in different regions. Customer-driven commands are short-lived, computation-complex, and extremely low-load functions. Accelerator templates can benefit from direct memory access, you can create a large number of operators in your work and operations. It can also operate on your site without the intervention of the handler.

A typical design process is to build a hardware platform for the user, develop a software platform for the micro-processor, regulate and identify the operation of the relevant operators, and use the HDL for implementation. hardware accelerator, and integrate the accelerator into the hardware platform, and then repeat the last three steps until they meet the performance requirements. However, using the c2h accelerator Compiler (C-to-hardware acceleration compiler ), developers can automatically generate hardware accelerators from their C program statements.

■ Niosⅱ C-to-hardware (c2h) to accelerate the zookeeper

In traditional systems, the method from C-to-Gates is used by enterprises to solve the problem of producing vertical hardware models, c2h is written in different ways, it uses the production assistant to unload and increase the processing efficiency of the processing tool on the microprocessor using the C language, this method can solve an important issue:

1. similar to the prototype of the computation that really accelerates the computation, or the C statement that has been written on a common micro-processor, or, the digital processing (DSP) component is tightly integrated in the internal programming process.

2. directly connect the hardware accelerator and processor memory ing.

3. Support for the scale and limit columns without permission.

4. efficiently record the delay in checking the progress and handling of the memory.

The actual behavior of this method can be supported by this tool system. Altera C-to-hardware acceleration (c2h) the memory generator can generate a hardware accelerator from the simplified ANSI/ISO Standard C language and directly access the memory and other memory accelerators in the processing system, the cycle and floating point form are the only functions excluded from the Standard C statement, which refer to the standard, rule column, architecture, and enums ), all routing and control components (including medium-definition "break", dynamic route "continue", and return "return" statements) are fully supported. C2h uses the intel, this will allow the accelerator to directly access the memory ing like a CPU, allowing the accelerator to port from the mirror to the hard, supports the metric and metric columns without permission. The c2h memory collector's console is the integrated CPU development environment, through support for the ANSI/iso c language of the Standards and non-extended standards, the c2h memory Reader allows the developer to use the processing tool to route data in the processing tool, in order to quickly generate a functional prototype, and then simply press a button, you can switch to a hardware-based acceleration.

■ C2h Design Process

The c2h design process starts with the C/C ++ programming case in the software IDE, and contains the ansi c language feature that has been provided for acceleration, you can also find the bottle name in the existing program and select the desired one for acceleration. The processing process is as follows:

1. perform prototype and release design in software IDE.

2. Provide the acceleration function for the selected targets in the IDE.

3. conduct c2h analysis on the acceleration function to generate some program warnings that may contain used resources, performance information, and c2h cannot be optimized, and the traffic-related information (such as the number of traffic-bearing devices attached to the number of connected devices. This process will take up to several seconds to minutes based on the degree of parallelism of the entire function and the sequence of average memory usage.

4. Optimization and agency calculation.

5. using the IDE, you can choose to generate updated component programs, and use traditional production tools to generate software updates for the entire system, and merge the information with the local communications authority in the design.

6. Upload the hardware image to the component.

7. Confirm the performance in the diagnostic program case. Currently, the hardware accelerator is used in the IDE.

This design process provides the ability of the user to segment the entire physical/hardware from the physical IDE, the actual line between the hardware model and the system, as well as the process of extracting with the processor, reporter and other operators. In addition, because the same ANSI/iso c statement is used in the development of the software and hardware, the user can immediately switch to the software to compile the function, rapid Analysis to accelerate or complete the process to generate an updated hard image. This provides a user tool to quickly repeat the division and optimization functions, without the need to perform synthesis and Optimization for a long period of time. (Provided by Altera)