Study Notes for Linux kernel 3rd-Chapter 2: memory addressing

In an 80x86 microprocessor-based computer, the memory addressing conversion process is: Logical Address → linear address (Virtual Address) → physical address. MMU (Memory Management Unit) involved in memory addressing has two important parts: Segment unit and paging unit. The former is responsible for converting logical addresses into linear addresses, the latter is responsible for converting linear addresses to actual physical addresses.

 

Hardware Segmentation

Each logical address contains two parts: a segment ID and a offset in the segment. This segment ID is the segment selector. The data structure has three fields: Index, Ti, and RPL. Ti = 0 indicates that the segment is saved in gdt of the Global Descriptor Table, and Ti = 1 indicates that the segment is saved in LDT of the Local Descriptor Table. A register is called a segment register, which saves the segment Selection Sub.
Each segment also has a segment descriptor (segment descriptor), which stores the basic attributes of the segment, such as the access permission and length. The base field of this segment descriptor can locate the linear address corresponding to this segment.

In Linux, there are two types of tables: gdt, LDT, and gdt. The two data structures store segment descriptors, they can be used to find the segment descriptor of a specific segment in the memory.

The addressing process is like this. Remove a segment from the segment register and select a sub. Multiply the index field of the sub-segment by 8 to get an offset, which is the index of the segment descriptor in gdt or LDT, the segment descriptor address of the segment is obtained through Ti, and the gdt or LDT address is obtained from the GDTR or ldtr register, and then the offset is added to obtain the segment descriptor address of the segment, then it is added to the offset in the segment in the logical address to obtain the linear address corresponding to the logical address. That is

When Ti = 0, linear ADDR = Index * 8 + [GDTR] + offset; otherwise, linear ADDR = Index * 8 + [ldtr] + offset

To convert logical addresses to linear addresses more quickly, 80x86 provides an unprogrammable register for storing segment descriptors, when a segment is selected as a sub-segment register, the segment descriptor address of the segment is loaded from the memory when the non-programmable register is used. In this way, the segment descriptor address can be obtained through unprogrammable registers without gdt or LDT, accelerating the address conversion process.

 

Hardware paging Mechanism

The paging unit is to convert a linear address to a physical address.

A linear address is divided into multiple blocks with a fixed length. Each block is called a page or page ), consecutive addresses on a page are also mapped to consecutive physical addresses.

The paging unit determines that Ram is divided into multiple pages with an equal-length frame. Each page contains a page.

The conventional paging method starts from 80386 and divides 32-bit linear addresses into three parts: Directory (10-bit high), table (10-bit middle), and offset (12-bit low ). In this way, each page has 2 to 12 power, that is, the size of 4 kb. At the same time, the CPU has a base address for storing the page Directory. In fact, the base address of the page Directory is associated with the process. The value of the base address is different for different processes.

The conventional paging uses two levels of paging. The addressing process is like this. The values in 1 and 3 (the base address of the page Directory) + the value of the linear address directory = the base address of the page table; 2. Base Address of the page table + value of the table in the linear address = physical address of the page box. The physical address of the page box contains data of a page; 3. base address + linear address offset = physical address. The data structure of the page directory contains the attribute bits of some page tables, and the data structure of the page table contains the attributes of some pages.

The principle of PAE (physical address extension) and 64-bit address paging is similar to that of conventional paging mode, and the 64-bit address is platform-dependent. This article does not describe it.

To reduce the negative efficiency caused by CPU memory access, high-speed cache is introduced in CPU and RAM Based on the "Locality Principle ".

80x86 also contains hardware called the conversion back-aid buffer (TLB) to accelerate linear address conversion. Each CPU has its own TLB, when a linear address is used for the first time, it calculates its physical address and stores the physical address in a TLB table. Each time a linear address is accessed, it can be quickly converted through TLB. When the CPU's Cr 3 register is modified, all TLB items of the CPU will be invalid.

 

Linux paging Mechanism

Starting from Linux 2.6.11, Linux unified the paging mechanism into a four-level paging mechanism based on different architectures and can adapt to PAE and 64-bit addresses. Its core idea is the same as that of conventional paging, only two data structures, page upper directory and page middle directory, are introduced in the middle.

In Linux 2.6.11 kernel source code, many macros and functions are defined to operate page table, page middle directory, page upper directory, and page global directory.

 

Physical address Layout

During Linux system initialization, the kernel must establish a physical address ing to specify which physical address ranges can be used by the kernel. Generally, the Linux kernel is loaded to the RAM with the physical address 0x00100000, and 1 MB of space is empty. This is because some empty space is used by BIOS.

In the early stages of system boot, the kernel requests the bios and obtains the size of the physical address. In modern computers, the kernel calls the BIOS process to create a physical address range table and its corresponding storage type.

Then the system calls the machine_specific_memory_setup (void) (include/asm-i386/Mach-default/setup_arch_post.h) function to create a physical address ing in which, obtain the memory ing information through the e820 table of BIOS. If you cannot obtain information from the e820 table, this function creates a memory ing table by default: The page box between 0x9f and 0x100 is marked as retained.

The setup_memory (void) function is called after machine_specific_memory_setup to analyze the physical address area and initialize some data to describe the physical address layout.

Process page table and kernel page table

The linear address of a process is divided into two parts: 0x00000000 ~ 0 xbfffffff (3 GB) User-state linear address and 0xc0000000 ~ 0 xffffffff (1 GB) Kernel linear address. The macro page_offset value is 0xc0000000 -- the start point of the kernel space.

The linear address mapped to the first part of the global directory table on the page is less than 0xc000000 (the first 768 Items are displayed when the PAE is not started, and the first three items are displayed after the PAE is started ), the remaining table items are the same for all processes and are the same as the corresponding table items in the global directory of the main kernel.

The kernel maintains its own page table, which is called the global directory of the main kernel page. When the kernel image is loaded into the memory, the CPU runs in the real mode, and the paging function is not enabled. The kernel initializes its own page table in two stages.

In the second phase, the kernel creates a limited address space, including the kernel code segment and kernel data segment, the initial page table, and the 1st kb space used to store the dynamic data structure, this space is only enough for the kernel to mount the core data structure initialized by the ram box.

In the 2nd phase, the kernel makes full use of the remaining Ram to create a page table (see "temporary kernel page table ").

Temporary kernel page table

The global directory of the temporary page is statically initialized during kernel compilation, while the temporary page table is initialized by the startup_32 function (ARCH/i386/kernel/head. s). At this time, the page upper directory and page middle directory are equivalent to the global directory items of the page.

The global directory of the temporary page is stored in the swapper_pg_dir variable, and the temporary page table is stored in the pg0 variable immediately after the initialized data segment in the kernel. It is assumed that the kernel, temporary page table, and the above-mentioned kb space can be accommodated in the first 8 MB of Ram space. To map 8 Mb space, the kernel requires two page table items.

The goal of the first phase of paging is to allow the 8 MB to be easily addressable in the real and protected modes. Therefore, the kernel creates a ing to replace 0x00000000 ~ 0x007fffff (8 m) and 0xc0000000 ~ Linear address 0xing of 0xc07fffff (8 m) to 0x00000000 ~ The physical address of 0x007fffff.

Then, the kernel fills all swapper_pg_dir items with 0 to create the desired ing, except 0th, 1, 0x300 (768), and 0x301 (769) these four table items. The initialization process is as follows:

• The address fields of item 0 and item 0 x are set to the physical address of pg0, while those of item 1 and item 0 x are set to the physical address of the page box following pg0.
• The present, read/write, and user/supervisor flag of these four items are set.
• The four accessed, dirty, PCD, PWD, and page size indicators are cleared.

At the same time, the paging unit is also enabled in the startup_32 function, that is, the address of swapper_pg_dir is written to the Cr 3 register, and the PG flag of the Cr0 register is set.