Summary of MII (Media independent interface media-independent interface)

 

MIIMedia independent interface (media-independent interface); or media-independent interface, which is the Ethernet industry standard defined by the IEEE-802.3. It includes a data interface and a management interface between MAC and PHY. Data interfaces include two independent channels used for the transmitter and receiver respectively. Each channel has its own data, clock, and control signal. The MII data interface requires a total of 16 signals. Management Interface (we use the serial management interface on the board,SMIIs a dual-signal interface: one is the clock signal, the other is the data signal (That is, MDC (clock), mdio (Data)). Through the management interface, the upper layer can monitor and control the phy. The MII (Management Interface) has only two signal lines.

The MII standard interface is used to connect Fast Ethernet MAC-block and PHY. "Media Independence" indicates that any type of PHY device can work properly without re-designing or replacing the Mac hardware. Interfaces working at other speeds are equivalent to MII: AuI (10 M Ethernet), gmii (Gigabit Ethernet), and xaui (10-Gigabit Ethernet ).

The MII bus specified in 802.3 is a universal bus used to connect different types of PHY to the same network controller (MAC. The network controller can use the same hardware interface to connect to any Phy.

Introduction to MII interfaces:

Ethernet Media interfaces: MII rmii smii gmii

All these interfaces come from MII. The MII (medium independent interface) means that the media is copper axis, optical fiber, cable, etc, this is because all of these media processing tasks are completed by the phy or Mac chip.

MII supports operations of 10 m and 100 m. An interface consists of 14 lines. Its support is flexible, but there is a disadvantage that it uses too many signal lines for a port, if a vswitch with eight ports needs 112 lines, port 16 requires 224 lines, and port 32 requires 448 lines. Generally, a vswitch is created based on this interface, it is not realistic, so modern switch production will use other standards simplified from MII, such as rmii, smii, and gmii.

Rmii is a simplified MII interface. In terms of data sending and receiving, it is twice the signal line of the MII interface, so it generally requires a 50 MB bus clock. Rmii is generally used in a multi-port switch. Instead of sending and receiving two clocks for each port, a clock is used for sending and receiving all the data ports, this reduces the number of ports. One rmii port requires seven data lines, which is twice less than MII, so the switch can access multiple data ports. Like MII, rmii supports 10 m and 100 M Bus Interface speeds.

Smii is a media interface proposed by Cisco. It has fewer signal lines than rmii, and s indicates serial. Because it only uses one signal line to transmit data and one signal line to transmit and receive data, in order to meet the requirement of 100, the clock frequency is very high, reaching 125 MB, why is 125 MB used? It is because some control information is transmitted in the data line. Smii only uses four signal lines to transmit 100 signals on one port, which is almost twice as short as rmii. Smii is strongly supported in the industry. Similarly, data transmission and receiving on all ports share the same external M clock.

Gmii is the MII interface of gigabit network, which also has the corresponding rgmii interface, indicating the simplified gmii interface.

How MII works:

"Media Independence" indicates that any type of PHY device works properly without re-designing or replacing the Mac hardware. Two independent channels are used for the transmitter and receiver respectively. Each channel has its own data, clock, and control signal.

MIIData InterfaceA total of 16 signals are required, including tx_er, txd, tx_en, tx_clk, Col, rxd, rx_ex, rx_clk, CRS, and rx_dv.

MII transmits data in four-byte bidirectional transmission with a clock rate of 25 MHz. The working rate can reach 100 Mb/s.

MII ManagerManagement InterfaceIt is a dual-signal interface, one is a clock signal, and the other is a data signal. Through the management interface, the upper layer can monitor and control the phy,Its management is implemented by using the SMI (Serial Management Interface) bus to read and write the register of the phy.

Some registers in the PHY are defined by IEEE. In this way, the PHY reflects its current status to the Register, mac constantly reads the Status Register of the PHY through the SMI bus to get the current PHY status, such as connection speed and duplex capability.

Of course, you can also set the register of the PHY through SMI to achieve the purpose of control. For example, if the throttling is enabled or disabled, the self-negotiation mode or the forced mode can be used.

Both the MII bus for physical connection and the State registers and control registers for the SMI bus and the PHY have IEEE specifications. Therefore, the Mac and the PHY of different companies can coordinate their work. Of course, in order to match the features specific to PHY of different companies, the driver needs to be modified accordingly.

Phy is a physical interfaceTransceiverIt implements the physical layer. Including the MII/gmii (Media independent interface) Sub-layer, PCs (physical encoding sub-layer), PMA (physical media attachment) Sub-layer, PMD (physical media-related) Sub-layer, and MDI sub-layer. 100basetx adopts 4b/5b encoding.

When sending data, phy receives data from MAC (for phy, there is no frame concept, and for it, it is data regardless of the address, data or CRC ), an Error Code of 1 bit is added for every 4 bits. Then, parallel data is converted into serial stream data, and the data is encoded according to the encoding rules of the physical layer. Then, the data is sent as a analog signal. Otherwise.

Another important feature of PHY is to implement some CSMA/CD functions.

It can detect whether data is being transmitted on the network. If data is being transmitted, it waits. Once it detects that the network is idle, it waits for a random time and sends the data out. If the two send data at the same time, a conflict will occur. At this time, the conflict detection agency can detect the conflict and wait for a random time to resend the data. This random time is very exquisite, not a constant. The random time calculated at different times is different, and there are multipleAlgorithmTo cope with the second conflict between the two hosts with low probability.

The communication rate is negotiated by both parties. The negotiation result is the maximum speed and the best duplex mode supported by both devices at the same time,This technology is calledAuto negotiation or Nway.

The isolating transformer filters the differential signals sent from the PHY using the differential mode coupled coils to enhance the signal, and couple the signals to the other end of the connected network through the electromagnetic field conversion.

In the RJ-45, 1, 2 are the data, and 3, 6 are the data.

The new PHY supports auto MDI-X functionality (The MDI/mdix auto-flip function enables you to use either a cross line or a direct line.), Also need to isolate transformer support, it can realize the RJ-45 interface on 1, 2 transmission signal line and 3, 6 receiving signal line function automatically exchange with each other.

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88f6282 project documents:

Hardware spec

P33: SMI interface pin assignments

Functional spec

P154: MII Interface

P161: SMI Interface

MV-S104224-00_88E1116R_Datasheet.pdf

P19: Mac interface (rgmii ),Data Interface

P61: hardware configuration

Hardware configuration phyad, which can be searched laterPhyadKeywords

This chip is configured through the pins connected by config pins (refer to P9)

P63: software configuration,Management Interface, SMI (Mido, and MDC)

P67: Register Configuration

See also:

MII

Http://en.wikipedia.org/wiki/Media_Independent_Interface

Management data input/output, orMDI

Http://en.wikipedia.org/wiki/Management_Data_Input/Output

 

 

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88f6282 SMI related functions

Mvethphy. c

/*************************************** ****************************************
* Mvethphyregread-read from Ethernet PHY register.
*
* Description:
* This function reads Ethernet PHY register.
*
* Input:
* Phyaddr-phy address.
* Regoffs-phy register offset.
*
* Output:
* None.
*
* Return:
* 16bit PHY register value, or 0 xFFFF on Error
*
**************************************** ***************************************/
Mv_status mvethphyregread (mv_u32 phyaddr, mv_u32 regoffs, mv_2010* data)
{
Mv_u32 smireg;
Volatile mv_u32 timeout;

/* check parameters */
If (phyaddr {< br> mvosprintf ("mvethphyregread: Err. illegal PHY device address % d \ n ",
phyaddr);
return mv_fail;
}< br> If (regoffs {< br> mvosprintf ("mvethphyregread: Err. illegal PHY register offset % d \ n ",
regoffs);
return mv_fail;
}

timeout = eth_phy_timeout;
/* Wait till the SMI is not busy */
DO
{
/* read SMI register */
smireg = mv_reg_read (eth_phy_smi_reg );
If (timeout -- = 0)
{< br> mvosprintf ("mvethphyregread: SMI busy timeout \ n");
return mv_fail;
}< BR >}while (smireg & eth_phy_smi_busy_mask);

/* Fill the PHY address and regiser offset and read opcode */
Smireg = (phyaddr <eth_phy_smi_dev_addr_offs) | (regoffs <eth_phy_smi_reg_addr_offs) |
Eth_phy_smi_opcode_read;

/* Write the SMI register */

/* Use the SMI register to manipulate the internal register of the PHY */
Mv_reg_write (eth_phy_smi_reg, smireg );

Timeout = eth_phy_timeout;

/* Wait till readed value is ready */
Do
{
/* Read SMI register */
Smireg = mv_reg_read (eth_phy_smi_reg );

If (timeout -- = 0 ){
Mvosprintf ("mvethphyregread: SMI read-valid timeout \ n ");
Return mv_fail;
}
} While (! (Smireg & eth_phy_smi_read_valid_mask ));

/* Wait for the data to update in the SMI register */
For (timeout = 0; timeout <eth_phy_timeout; timeout ++ );
* Data = (mv_2010) (mv_reg_read (eth_phy_smi_reg) & eth_phy_smi_data_mask );

Return mv_ OK;
}

/*************************************** ****************************************
* Mvethphyregwrite-write to Ethernet PHY register.
*
* Description:
* This function write to Ethernet PHY register.
*
* Input:
* Phyaddr-phy address.
* Regoffs-phy register offset.
* Data-16bit data.
*
* Output:
* None.
*
* Return:
* Mv_ OK if write succeed, mv_bad_param on bad parameters, mv_error on error.
* Mv_timeout on timeout
*
**************************************** ***************************************/
Mv_status mvethphyregwrite (mv_u32 phyaddr, mv_u32 regoffs, mv_2010data)
{
Mv_u32 smireg;
Volatile mv_u32 timeout;

/* check parameters */
If (phyaddr {< br> mvosprintf ("mvethphyregwrite: Err. illegal PHY address \ n ");
return mv_bad_param;
}< br> If (regoffs {< br> mvosprintf ("mvethphyregwrite: Err. illegal register offset \ n ");
return mv_bad_param;
}< br> timeout = eth_phy_timeout;

/* Wait till the SMI is not busy */
DO
{
/* read SMI register */
smireg = mv_reg_read (eth_phy_smi_reg );
If (timeout -- = 0) {
mvosprintf ("mvethphyregwrite: SMI busy timeout \ n");
return mv_timeout;
}< BR >}while (smireg & eth_phy_smi_busy_mask);

/* Fill the PHY address and regiser offset and write opcode and Data */
Smireg = (Data <eth_phy_smi_data_offs );
Smireg | = (phyaddr <eth_phy_smi_dev_addr_offs) | (regoffs <eth_phy_smi_reg_addr_offs );
Smireg & = ~ Eth_phy_smi_opcode_read;

/* Write the SMI register */
Mv_reg_write (eth_phy_smi_reg, smireg );

Return mv_ OK;

}