The paging mechanism of Linux memory addressing

Http://blog.xiaohansong.com/2015/10/05/Linux memory addressing paging mechanism/

In the previous article, in the segment mechanism of Linux memory addressing, we learned about the process by which a logical address is transformed into a linear address through a fragmentation mechanism. Below, let's look at the more important and complex paging mechanism.

The paging mechanism is performed after the segment mechanism to complete the linear-physical address conversion process. The segment mechanism translates the logical address into a linear address, and the paging mechanism further transforms the linear address into a physical address.

Paging in hardware

The paging mechanism is enabled by the PG bit in CR0. such as pg=1, the paging mechanism is enabled, and the linear address is converted to a physical address using the mechanism described in this sectionto. such as pg=0, disable paging mechanism, directly to the segment mechanism generated by the linear address as a physical address use. The paging mechanism manages objects that are fixed-sized blocks of storage called pages (page). The paging mechanism sees the entire linear address space and the entire physical address space as composed of pages, and any page in the linear address space can be mapped to any page in the Physical address space (we call a page or page frame in the physical space)

80386 pages that use 4K byte size. Each page has a length of 4 K bytes and is aligned on a 4K byte boundary, that is, the starting address of each page is divisible by 4 K. As a result, 80386 4G bytes of linear address space, divided into 1M pages, each page has 4 K-byte size. The paging mechanism is managed by relocating the pages in the linear address space to the physical address space, because the entire 4K bytes of each page are mapped as one unit, and each page aligns to the bounds of the 4K byte, so the low 12-bit linear address is used directly as a low 12-bit of the physical address by a paging mechanism.

Why use a Level two page table

Assuming that each process consumes 4G of linear address space, the page table contains a total of 1M table entries, and each table entry occupies 4 bytes, the page table for each process occupies 4M of memory space. To save space on the page table, we use the Level two page table. Each process is assigned a page directory, but only the actual use of the page table will be allocated to the memory. The first-level page table needs to allocate all the page table space at once, and the Level two page table can then allocate the page table space when needed.

Level two page table structure

The first level of the two-level table structure is called the page directory, which is stored in a 4K-byte page. The page catalog table has a total of 1K table entries, each of which is 4 bytes and points to the second-level table. The highest 10 bits of the linear address (the ascended 31~ bit 32) are used to produce the first level of the index, and a table in the 1K level two table is specified and selected by the indexed table entry.
The second level of the two-level table structure, called the page table, is also stored exactly in a 4K-byte page, containing a 1K-byte table entry, each containing a physical base address for the page. The second-level page table is indexed by the middle 10 bits of the linear address (the ascended 21~ bit 12) to obtain a page table entry containing the physical address of the page, where the high 20 bits of the physical address and the low 12 bits of the linear address form the final physical address, the physical address of the output of the page conversion process.
Level two page table structure

Page Catalog Item

Page Catalog Item Structure

• The 31st to 12th bit is the 20-bit page table address, because the low 12 bits of the page table address are always 0, so it is possible to indicate the 32-bit page table address with the high 20 bits. Therefore, a page directory contains a maximum of 1024 page table addresses.
• The No. 0 bit is the presence bit, if p=1, that indicates that the page table address points to the page in memory, and if p=0, the representation is not in memory.
• The 1th bit is the read/write bit, and the 2nd bit is the user/administrator bit, which provides hardware protection for the page catalog entries. Two bits. When a process with a privileged level of 3 wants to access a page, a page guard check is required, and a process with a privileged level of 0 can bypass page protection.
• The 3rd bit is the PWT (Page write-through) bit, which indicates whether the write-through method is written in both memory (RAM) and write cache, which is 1 for write-through mode
• The 4th bit is the PCD (Page Cache Disable) bit, which indicates whether the cache is enabled, and the bit is 1 to enable caching.
• The 5th bit is the access bit, when access to the page catalog item, a bit = 1.
• The 7th bit is the page size flag, which applies only to pages catalog items. If set to 1, the page directory entry refers to the 4MB page, see the extended pagination later.
• The 9th to 11th bit is dedicated to the operating system, and Linux has no special use.

Page Item

Page Item Structure
80386 each page catalog entry points to a page table with a maximum of 1024 page items, 4 bytes per item, containing the starting address of the page and information about the page. The starting address of the page is also an integer multiple of 4 K, so the lower 12 bits of the page are also reserved for use.
The 31st to 12th bit is the 20-bit physical page address, except for the 6th digit No. 0 to 5th bit and the 9~11 bit for the same purpose as the page catalog item, the 6th bit is unique to the page item, and when the involved page is written, the D bit is set to 1.
4GB of memory has only one page directory, it has a maximum of 1024 page catalog items, each page catalog item also contains 1024 page items, so memory can be divided into 1024x1024=1m pages altogether. Because each page is 4K bytes, the memory size is exactly 4GB.

Linear address-to-physical address conversion

32-bit linear address-to-physical address conversion

1. CR3 contains the starting address of the page directory, with the top 10 bits of the 32-bit linear address as the index of the page directory entry for the page directory, multiply it by 4, and the starting address of the page directory in CR3, to form the address of the corresponding page table.
2. Remove the 32-bit page directory entry from the specified address, which has a low 12 bit of 0, and 32 bits is the starting address of the page table. Use the A21~A12 bit in a 32-bit linear address as the index of the page in the page table, multiply it by 4, and add the starting address of the page table to form a 32-bit page address.
3. The a11~a0 is added as a offset from the page address to the 32-bit page address to form a 32-bit physical address.

Extended Paging

Starting with the Pentium processor, Intel microprocessors introduced extended paging, which allowed the page size to be 4MB.
Extended Paging
In the case of extended paging, the paging mechanism divides a 32-bit linear address into two domains: the highest 10-bit directory domain and the remaining 22-bit offsets.

Page cache

Page cache
Because of the paging situation, each memory access to access the Level two page table, which greatly reduces the access speed. So, to speed up, set up a cache hardware mechanism for a recently accessed page in 386, which automatically maintains the most recent page address for 32 processors, so it can overwrite the memory address of a 128K byte. When making memory access, first check whether the page to be accessed is in the cache, and if so, you do not have to go through two levels of access, if not, then level two access. On average, the page cache has a hit rate of about 98%, meaning that only 2% of the time a memory is accessed must have access to a two-page paging mechanism. This greatly accelerates the speed.

Paging mechanism in Linux

Linux uses a paging mechanism that is suitable for 32-bit and 64-bit systems.
Linux Paging model

• Page Global Catalog
• Page top-level directory
• Page Intermediate Directory
• Page table

The page global catalog contains the addresses of several pages of the ancestor directory, which in turn contains the addresses of several pages in the intermediate directory, and the middle of the page contains the addresses of several page tables. Each page table entry points to a single page box. The linear address is therefore divided into five parts. The number of digits is not shown in the figure because the size of each part is related to the specific computer architecture.

A Level Two page table is sufficient for 32-bit systems that do not have physical Address extensions enabled. In essence, Linux completely cancels the page ancestor directory and the page Intermediate directory field by making the page ancestor directory bit and the "page Intermediate directory" bit all 0. However, the position of the page ancestor directory and the page intermediate directory in the pointer sequence is preserved so that the same code can be used under both 32-bit and 64-bit systems. The kernel retains a location for the page ancestor directory and the page intermediate directory by setting their page directory entries to 1 and mapping the two directory entries to a suitable directory entry for the page's global catalog.

A 32-bit system with physical Address extensions enabled uses a Level three page table. The Linux page global catalog corresponds to the 80x86 page directory pointer table (PDPT), cancels the page parent directory, the page intermediate directory corresponds to the 80x86 page directory, and the Linux page table corresponds to the 80x86 page table.

Finally, 64-bit systems use three-level or four-level paging depending on the hardware's division of the bits of the linear address.

Summarize

Here we do not discuss code implementation, only focus on the principle. From the discussion above, you can see that the paging mechanism relies primarily on hardware implementations. Linux uses the Level four page table just to maximize the compatibility of different hardware implementations, single-IA32 architecture of the CPU, there are a variety of paging implementation, the general paging mechanism, PAE mechanism.

While we're talking about the paging mechanism of Linux, we've actually used most of the space to discuss the implementation of the paging mechanism for Intel CPUs. Because the paging mechanism of Linux is based on hardware, different platforms need different implementations. Linux at the software level to construct the virtual address, and ultimately through the MMU into a physical address, that is, regardless of how the Linux paging mechanism is implemented, the CPU only according to its paging implementation to interpret the linear address, so the linear address of Linux to the CPU is bound to meet the hardware implementation. For example: Linux on a 32-bit CPU, its four-level page table structure is compatible with the hardware of the two-level page table structure. As can be seen, Linux is a layer of abstraction on the software level, with a four-level page table compatible with 32-bit and 64-bit CPU memory addressing different hardware implementations.

Finally, we share two experimental documents of Linux memory addressing, which is easier to understand with examples.
Linux Memory address mapping
Linux kernel address mapping in x86_64 CPU

Resources
Deep understanding of the Linux kernel
Deep analysis of the Linux kernel source code

The paging mechanism of Linux memory addressing