Using glade and GTK + to develop C-language interface programs under Ubuntu (iii)--Learn how to use make

the rules of makefilethe rules of Makefile are as follows:

Target ...: Prerequisites ... command ....

Target can be either an object file or an executable file, or it can be a label.prerequisites is to generate the files or targets needed for that target. command is what the make needs to execute. (Arbitrary shell command)The relationship between these three is a file dependency, target one or more object files are dependent on the files in the prerequisites, and their generation rules are defined in the command. The main meaning of this is that if more than one file in the prerequisites is newer than the target file, command-defined commands are executed. This is the core content of makefile. A simple examplea project has 3 header files, 8 c files, and the following makefile defines the rules for this project compilation.

EDIT:MAIN.O kbd.o command.o display.o insert.o search.o files.o utils.occ-o edit main.o kbd.o command.o display.o inser T.O search.o files.o utils.omain.o:main.c defs.hcc-c main.ckbd.o:kbd.c defs.h command.hcc-c Kbd.ccommand.o:command . C defs.h command.hcc-c command.cdisplay.o:display.c defs.h buffer.hcc-c display.cinsert.o:insert.c defs.h BUFFER.HC C-c insert.csearch.o:search.c defs.h buffer.hcc-c search.cfiles.o:files.c defs.h buffer.h command.hcc-c files.cutil S.O:UTILS.C defs.hcc-c utils.cclean:rm Edit main.o kbd.o command.o display.o insert.o search.o files.o UTILS.O

Save the above content as a file named "Makefile" or "makefile", directly to the command line into the directory of this file, execute make command, you can generate the required executable file edit, if you want to delete the execution file and all intermediate files, A simple make-clean command.in the above makefile, the target file contains: Execute file Edit and intermediate target file (*.O), the dependent file (prerequisites) is the. c file and the. h file after the colon. At the same time, it can be seen that each of the. o files have a set of dependent files, and these. o files are also dependent files that execute file edit, and the dependency is essentially a description of which files are generated by the target file. after the dependencies are clear, the following line defines the system commands for generating the target file, which begins with a TAB key. This is a particular area to note. Make no matter how the command works, it executes the commands you have written, and makes compares the modified date of the target file and the prerequisites file, if the date of the prerequisites file is newer than the targets file date, Or if the target file does not exist, make executes the command. The final definition of clean is not a file, just a command name, make does not go to the clean dependent file, followed by no dependent files, to execute the clean command, you need to indicate the command name in the command, such as Make clean, This clean is the label, and make will find the corresponding command in its file that is under the clean tag to execute the corresponding command. how make Worksin the default mode, we only need to enter the make command. 1. Make will find the file named "Makefile" or "Makefile" in the current directory. 2, if found, it will find the file in the first target file (target), in the makefile file above it will find "edit" This file, and put this file as the final target file. 3, if the edit file does not exist, or edit after the. o File modification time is newer than the edit file, then he will execute the commands defined later to generate this edit file. 4. If the above. o file does not exist, then make will find the dependency of the. o file in the current file, and finally execute the command to generate the corresponding. o file. 5. If you can find the. h file and the. c file, then make executes its command to eventually generate the target file, edit. the way it works is a layer of dependencies. Make makes the search for the required files in the current folder based on the specific dependencies, and if the required files cannot be found, then it exits directly. and error, errors for the defined command, or the compilation is unsuccessful. Make does not care about these things, made just executes the commands that you define according to the dependencies of the defined files, and if there is a mistake in the middle, you exit without executing the command. In the above rules, such as clean does not rely on file relations, followed by only one command, when the execution of the command will not be executed, but can be displayed after make the declaration of this command to execute. For example, make clean, which executes the commands defined in the cleanup and cleans up all intermediate and target files that are generated to facilitate recompilation. in the process of compiling, if the project has been compiled, and when we have modified one of the files, then according to the make rules, make will not compile the other already generated target files, wisdom recompile the modified file, and generate the final target file, This is make, although those dependent on the file time is newer than the time of the target file, then the file will be recompiled, other regardless, and eventually linked to the desired final target file edit. Using Variables in Makefilein the example above, we can see that the dependent files followed by the edit and the commands in the ". O" file were repeated two times, If we are going to introduce an. o file, or modify the name of an. o file, then we need to modify three places, edit there are two, and the following one. o file, which is easy to modify in small projects, but if a project is relatively large, then makefile will be relatively large and complex, then it is possible to forget to modify a A place. So in order to makefile easy to maintain, in makefile can use variables, makefile variables are actually defined some strings, can be understood as the C language macro definition. For example, we can declare some variables to represent the target file, such as: Object,obj,objects. You can define variables as follows in makefile.

objects = MAIN.O kbd.o command.o display.o insert.o search.o files.o UTILS.O

Then we can use this variable in makefile in the form of "$ (objects)". So makefile can be changed to the following way:

objects = MAIN.O kbd.o command.o display.o insert.o search.o files.o utils.oedit: $ (objects) Cc-o edit $ (objects) MAIN.O: MAIN.C defs.hcc-c main.ckbd.o:kbd.c defs.h command.hcc-c kbd.ccommand.o:command.c defs.h command.hcc-c COMMAND.CDI SPLAY.O:DISPLAY.C defs.h buffer.hcc-c display.cinsert.o:insert.c defs.h buffer.hcc-c insert.csearch.o:search.c def S.h buffer.hcc-c search.cfiles.o:files.c defs.h buffer.h command.hcc-c files.cutils.o:utils.c defs.hcc-c utils.ccle AN:RM Edit $ (objects)

This allows us to modify the [. O] File simply by modifying it in the variable objects. Rules for emptying file targetsEach makefile should have a purge target file (. O and Executables), which is not only easy to compile, but also keeps the file clean. the general emptying rules are as follows:

CLEAN:RM Edit $ (objects)

A more robust approach is as follows:

. Phony:cleanclean:-rm Edit $ (objects)

. Phony means that clean is a "pseudo-target". A minus sign in front of the RM command means that some files may have problems, but do not care, continue to do the following, of course, clean rules are generally placed in the makefile of the final document, which is also an unwritten rule.
of course, here are just a few simple knowledge of make, which is enough to write some small system compilation, if interested students can find a special introduction to make books to read, deepen their understanding of make.

Using glade and GTK + to develop C-language interface programs under Ubuntu (iii)--Learn how to use make