Write Linux makefile

I. makefile rules

Before talking about this makefile, let's take a rough look at the makefile rules.

Target...: prerequisites...

Command

...

...

Target is a target file, which can be an object file or an execution file.

Prerequisites is the file or target required to generate the target.

Command is the command to be executed by make. (Any shell command)

This is the dependency of a file. That is to say, one or more target files depend on the files in prerequisites, and their generation rules are defined in command. To put it bluntly, if prerequisites has

If more than one file is newer than the target file, the command defined by command will be executed. This is the makefile rule. That is, the core content in makefile.

Ii. Example

As mentioned above, if a project has three header files and eight C files, we want to complete the three rules described above, our makefile should look like the following.

Edit: Main. o kbd. O command. O display. O/

Insert. O search. O files. O utils. o

Gcc-O edit main. o kbd. O command. O display. O/

Insert. O search. O files. O utils. o

Main. O: Main. c defs. h

Gcc-C main. c

KBD. O: KBD. c defs. H command. h

Gcc-c kbd. c

Command. O: Command. c defs. H command. h

Gcc-C command. c

Display. O: Display. c defs. h buffer. h

Gcc-C display. c

Insert. O: insert. c defs. h buffer. h

Gcc-C insert. c

Search. O: search. c defs. h buffer. h

Gcc-C search. c

Files. O: files. c defs. h buffer. H command. h

Gcc-C files. c

Utils. O: utils. c defs. h

Gcc-C utils. c

Clean:

Rm edit main. o kbd. O command. O display. O insert. O search. O files. O utils. o

A backslash (/) indicates a line break. This makes it easier to read makefile. We can save this content in a file named "makefile" or "makefile", and then directly enter the command "make" in this directory.

You can generate the execution file edit. If you want to delete the execution file and all the intermediate target files, simply execute "make clean.

In this makefile, the target file contains the execution file edit and intermediate target file (*. o), the dependent files (Prerequisites) are the ones after the colon. c file and. h file. Every. o file has

A group of dependent files, and these. O files are dependent files for execution file edit. The dependency essentially describes the files generated by the target file, in other words, the files updated by the target file.

After the dependency is defined, the subsequent line defines how to generate the operating system commands for the target file, which must start with a tab key. Remember, make does not care about how the command works. It only executes the defined command.

Make will compare the modification date of the targets file and the prerequisites file. If the date of the prerequisites file is newer than the date of the targets file, or the target does not exist, make will execute the subsequent definition

Command.

It should be noted that clean is not a file, it is just an action name, a bit like lable in C language, and there is nothing after the colon, so, make will not automatically find the dependency of the file, so it will not

The command defined after the execution. To execute the subsequent command, you must clearly name the lable after the make command. This method is very useful. We can define unnecessary compilation in a makefile or it has nothing to do with compilation.

Such as program packaging, program backup, and so on.

3. How does make work?

By default, we only enter the make command. So,

1. Make will find the file named "makefile" or "makefile" in the current directory.

2. If it is found, it will find the first target file (target) in the file. In the above example, it will find the file "edit, and use this file as the final target file.

3. If the edit file does not exist or is later than the edit file. O if the file modification time of the file is newer than that of the edit file, the file will be generated by executing the command defined later.

4. If. o file does not exist, so make will find the target in the current file. o file dependency. If found, it will be generated based on that rule. o file.

5. Of course, your c files and H files exist, so make will generate. o file, and then use. o The ultimate task of file life make, that is, execution file edit.

This is the dependency of the entire make. Make will find the dependency of the file layer after layer until the first target file is finally compiled. If an error occurs during the search process, for example, the dependent file cannot be found

Make will exit directly and report an error. Make will ignore the errors of the defined command or the compilation fails. Make only depends on the dependency of the file. That is, if the file after the colon is not found after I find the dependency

Sorry, I am not working.

Through the above analysis, we know that such commands as clean are not directly or indirectly associated with the first target file, and the commands defined after it will not be automatically executed. However, we can show that you want to execute make. That is, the command --

"Make clean" to clear all target files for recompilation.

So in our programming, if this project has been compiled, when we modify one of the source files, such as file. c. Then, based on our dependencies, our target file. O will be re-compiled (that is, after this dependency

Command defined by), so file. O files are also up-to-date, so file. o file modification time is newer than edit, so edit will be relinked.

If we change "command. H", KDB. O, command. O, and files. O will be recompiled, and edit will be relinked.

4. Use variables in makefile

In the above example, let's take a look at the edit rules:

Edit: Main. o kbd. O command. O display. O insert. O search. O files. O utils. o

Gcc-O edit main. o kbd. O command. O display. O insert. O search. O files. O utils. o

We can see [. o] the file string is repeated twice. If our project needs to add a new [. o] file, so we need to add it in two places (three places, and one place in clean ). Of course, I

Their makefile is not complex, so it is not tiring to add it in two places. However, if the makefile becomes complex, we may forget a place to be added, leading to compilation failure. Therefore, to make makefile easy to maintain,

Variables can be used in makefile. The makefile variable is a string, which may be better understood as a macro in C language.

For example, we declare a variable named objects, objects, objs, objs, OBJ, or obj. Whatever it is, you just need to be able to represent the OBJ file. We defined this at the beginning of makefile:

Objects = Main. o kbd. O command. O display. O/

Insert. O search. O files. O utils. o

Therefore, we can easily use this variable in the "$ (objects)" method in our makefile, so our improved makefile will look like the following:

Objects = Main. o kbd. O command. O display. O/

Insert. O search. O files. O utils. o

Edit: $ (objects)

Gcc-O edit $ (objects)

Main. O: Main. c defs. h

Gcc-C main. c

KBD. O: KBD. c defs. H command. h

Gcc-c kbd. c

Command. O: Command. c defs. H command. h

Gcc-C command. c

Display. O: Display. c defs. h buffer. h

Gcc-C display. c

Insert. O: insert. c defs. h buffer. h

Gcc-C insert. c

Search. O: search. c defs. h buffer. h

Gcc-C search. c

Files. O: files. c defs. h buffer. H command. h

Gcc-C files. c

Utils. O: utils. c defs. h

Gcc-C utils. c

Clean:

Rm edit $ (objects)

So if a new. o file is added, you only need to modify the objects variable.

V. Make auto-Derivation

GNU make is very powerful. It can automatically deduce the commands behind the file and file dependency, so we do not need to go to every [. o] similar commands are written after the files, because our make will automatically identify and deduce our own

.

As long as make sees [. o] file, it will automatically [. c] Add the file to the dependency. If make finds a whatever. o, then whatever. c, it will be whatever. o. And CC-C

Whatever. C will also be deduced, so our makefile no longer needs to be written in such a complex way. The new makefile will be changed.

Objects = Main. o kbd. O command. O display. O/

Insert. O search. O files. O utils. o

Edit: $ (objects)

CC-O edit $ (objects)

Main. O: defs. h

KBD. O: defs. H command. h

Command. O: defs. H command. h

Display. O: defs. h buffer. h

Insert. O: defs. h buffer. h

Search. O: defs. h buffer. h

Files. O: defs. h buffer. H command. h

Utils. O: defs. h

Clean:
Rm edit $ (objects)

6. Rules for clearing the target file

Each makefile should write a rule to clear the target file (. O and execution file), which not only facilitates re-compilation, but also facilitates file cleaning. The style is as follows:

Clean:

Rm edit $ (objects)

A more robust approach is:

. Phony: clean

Clean:

-RM edit $ (objects)

. Phony indicates that clean is a "pseudo target ",. The addition of a small minus sign in front of the RM command means that some files may have problems, but don't worry, continue to do the following. Of course, the clean rule is not

Put it at the beginning of the file. Otherwise, it will become the default target of make. The unwritten rule is: "clean is always placed at the end of the file ".

Reproduced in: http://bbs.dameng.com/viewthread.php? Tid = 1506