Analysis on the interview of Embedded Linux (i.)--arm PART II

analysis of embedded Linux interview (I.)--ARM Part II

1. describe how the embedded ROM-based operation is based on RAM What is the difference between the operating mode.

RAM-based operation: the hard disk and other media need to be loaded into the RAM, loading process generally has relocation operations;

Rom based: no above operation.

ROM-based: Slower than ram-based, because there will be a variable, part of the code, such as moving from memory (hard disk, Flash) to the RAM process; available RAM resources are more than RAM-based;

RAM-based: faster than ROM-based, available RAM is less than ROM-based, because all code, data must be stored in RAM.

2. What is the difference between an embedded operating system and a general operating system?

Answer: Multi-priority, preemptive type, real-time operating system. The embedded operating system generally has no UI, small size, strong real-time, and higher stability requirements. The embedded operating system emphasizes real-time and can be cut. Requires that the system resources be consumed as little as possible.

3. In the arm architecture, what is the method to switch from active user mode (user) to Super User mode (Supervisor)? C
A, directly modify the CPU status register (CPSR) corresponding mode
B, first modify the program state Backup register (SPSR) to the corresponding mode, and then update the CPU state
C. Using software interrupt instruction (SWI)
D. Let the processor execute undefined instructions

4. In the arm Linux system, the exception mode used to handle peripheral interrupts is __c____
A, software interrupt (SWI) B, undefined instruction exception
C, interrupt request (IRQ) D, fast interrupt request (FIQ)

5. in an ARM Linux system, when the interrupt handler enters C code, ARM is in the __a__ mode of Operation
A, Super User (SVC) B, interrupt (IRQ)
C, Fast Interrupt (IRQ) D, and the state before entering the interrupt is related

6. In an embedded system built by the arm system, when the interrupt is triggered by the level mode, when should the corresponding interrupt standard be cleared? A
A, when the interrupt handler is finished, you can clear the
B, enter the corresponding interrupt handler, that is, you can clear the
C, when an IRQ interrupt occurs, the processor automatically clears
D, can be cleared at any time

7. In the various modes of the following ARM processors, only the __a___ mode is not free to change the operating mode of the processor.
A, User mode (subscriber) B, System mode
C, termination mode (Abort) D, interrupt mode (IRQ)

8.                           in an arm embedded system, the PC points to the instruction address being (C).
A performs B decoding C refers to D is not

9. which of the following is not a feature of RISC processors compared to CISC ___d_____
A, the use of fixed-length instruction format, the instructions are structured, simple, basic addressing methods have two or three kinds.
B, reduce the number of instructions and addressing methods to simplify the control components, speed up the execution speed.
C, the data processing instruction only registers the operation, only the load/storage instruction can access the memory, improves the instruction execution efficiency, simultaneously simplifies the processor design.
D, RISC processors are based on the Harvard structure

10. In the arm architecture, what is the method to switch from active user mode (user) to Super User mode (Supervisor)? C
A, directly modify the CPU status register (CPSR) corresponding mode
B, first modify the program state Backup register (SPSR) to the corresponding mode, and then update the CPU state
C. Using software interrupt instruction (SWI)
D. Let the processor execute undefined instructions

11. in ARM system structure, the smallest unit space of MMU mapping is __d__
A, 64KB B, 16KB C, 4KB D, 1KB

in the process of ARM Linux startup, when the MMU is opened, how to realize the excess of the actual address space to the virtual address space? D

13. In the arm Linux system, the exception mode used to handle peripheral interrupts is _c_____
A, software interrupt (SWI) B, undefined instruction exception
C, interrupt request (IRQ) D, fast interrupt request (FIQ)

14.                                instruction Add R2,R1,R1,LSR #2中, the meaning of the LSR is (B).
A logical left Shift B logical right Shift C arithmetic right shift D loop right shift

15. the difference between the Harvard structure and the von Neumann structure is (A)
A instruction and data separate storage B do not need program counter C Unified address D single data bus

16. the important difference between ARM9 and ARM7 is (A)
A ARM9 with MMU function B ARM9 support thumb instruction Set
C ARM9 with cache function D ARM9 is the Harvard structure

17. When the system workload increases, the CPU a will account for a large proportion
A) User Time B) system time C) idle time D) process time

18. the embedded microcontroller has the greatest characteristics compared to the embedded microprocessor (B).
A, the volume greatly reduced B, monolithic
C, low power consumption D, high cost

19. which of the following is not a feature of RISC processors compared to CISC __d______
A, the use of fixed-length instruction format, the instructions are structured, simple, basic addressing methods have two or three kinds.
B, reduce the number of instructions and addressing methods to simplify the control components, speed up the execution speed.
C, the data processing instruction only registers the operation, only the load/storage instruction can access the memory, improves the instruction execution efficiency, simultaneously simplifies the processor design.
D, RISC processors are based on the Harvard structure

20. the interrupt vector refers to (C).
A, address B of the Mana Point, Interrupt vector table start address
C, interrupt handler entry address D, interrupt return address

21. in ARM system structure, the largest unit space of MMU mapping is ___a_
A, 1MB B, 128KB C, 64KB D, 4KB

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Analysis on the interview of Embedded Linux (i.)--arm PART II