Android camera (II): Camera working principle, s5pv310 camera interface (camif)

Keywords:Camif parameter of the android camera CMM Module
Platform information:
Kernel:Linux
System:Android

Platform:S5pv310 (Samsung exynos 4210)

Author: xubin341719 (You are welcome to reprint it. Please note the author)

Android camera (1): CMM introduction to the camera Module

Android camera (II): Camera working principle, s5pv310 camera interface (camif)

Android camera (III): Camera v4l2 fimc

Android camera (iv): camera driver gt2005

Download: Common camera specifications (some Android drivers): Bf3703 30 W, gc0308 30 W, ov7670, gt2005 200 W, gt2015 200 W, nt99250 200 W, s5k5ba 200 W, s5k4ba

I. How cameras work

In the previous article, we talked about the composition and working principle of the camera module. Next we will analyze how the camera works from the register perspective. Read the camera specifications (key parameters are used for driver adjustment. Take gt2005 as an example ).

The specification, that is, all the descriptions of a device, is accurate to every detail of the device, registers of concern to the software, electrical characteristics of concern to the hardware, encapsulation, and so on. In terms of driver alone, we can only look at the useful aspects for us, and there is no need to read them all. In this case, all the materials are in the bird's language (en). On the one hand, it will take a lot of time to finish reading them. Just find the key point.

1. The overall situation of camera is as follows:The Control Department is divided into the camera power-on and IIC control interfaces. The data output is a picture taken by the camera and transmitted to the master chip. All data, field synchronization, and clock numbers are required. Gt2005/gt2015 is an image sensor chip with a CMOS interface. It can sense external visual signals and convert them into digital signals and output them.

We need to use the mclk to provide the camera with a clock. The Reset is a reset line, and the pwdn should always be low when the camera is working. Pclk is the pixel clock, href is the row reference signal, and vsync is the field synchronization signal. Once the camera provides a clock and resets the camera, the camera starts to work and transmits Digital Image Signals synchronously through href, vsync, and pclk. Data is transmitted through D0 ~ D7 data lines are concurrently sent.

(1) pixel array

The size of the gt2005 array is 1268 columns, 1248 rows, 1616 columns of valid pixels, and 1216 rows. That is to say, when the camera is x1200, there are more pixels than this. remove part of the edge to ensure image quality.

(2) IICNeedless to say, the camera register initialization data is transmitted from here, and all IIC devices work the same way. Let's take a picture and make a detailed analysis later;

The following sections are important in the driver debugging process:

(3) mclk

Electronic components require a clock. Cameras need to work. This is the clock we want. The clock must be provided on the master control chip. Otherwise, the camera will not work.

(4) Timing of power-on and power-off, This is to be followed up by the specifications. The pwdn and resetb ports are different from the camera. This figure shows the timing of power-on. Refer to it when power-on and know where to look;

(5) pclk \ d1 ~ D7

The data obtained by the camera must be transmitted. Of course, the data may be sent out in minutes and at the same time as the time sequence displayed by the LCD. The principle is the same:

(6) main registers: resolution, YUV sequence, X axis, Y axis mirror phase, flip

After the above work is completed, there may be some problems, the resolution is too small, the YUV sequence is not correct, the XY image direction. After these tasks are completed, if you have any details, if you want to spend time reading the registers in the spec book, you can solve them. If you don't want to check the details, find the Fae in the module factory, they are professional and will soon help you.

(7) Hardware Interfaces of cameras

Ii. hardware interface on camera master chip on s5pv310

1. camif camera interface

First, let's take a look at the camera interface diagram: (this looks a bit like a figure. Let's take a look at it here. In fact, this is generally not involved in the driver, but we analyzed it here and brought it out)

(1) main attributes of the camera interface:

A. Multiple Input interfaces are supported: (the four modes we see above)

DMA (Axi 64-bitinterface) mode;

Mipi (CSI) mode;

ITU-R BT 601/656/709 mode;

Direct FIFO (playback) mode;

B. Multiple output modes are supported:

DMA (Axi 64-bitinterface) mode;

Direct FIFO mode;

C. supports digital zoom in (dzi) capability;

D. Multi-camera input is supported;

E. Supports polarity Programmable Control of Video Synchronization signals;

F. The maximum input resolution is 8192x8192;

G. Supports image flip (X axis, Y axis mirror phase, 90, 180, 270 flip );

H. Multiple image formats are supported;

I. Supports frame capture control;

J. Supported image effects.

2. fimc fully interactivemobile camera

The data collected by the camera cannot be directly processed by the CPU. The master chip is integrated with the camera Controller called fimc (fullyinteractive Mobile Camera ). The camera must first transmit the image data to the Controller, and then process it with the CPU after the Controller completes processing (cropping and pulling, directly previewing or encoding. In fact, the clock needed for camera operation (mclk) is also provided by fimc.

The camera interface on s5pv310 is a fimc (fully interactive mobile camera interface) that supports the itur BT-601-605 standard, AMX interface, mipi Interface

Mipi, ITU, AMX

(1) ITU International Telecommunication Union radio communication departmentITU-rradiocommunication Sector of ITU ITU-RITU-R (bt.601)16-bit data transmission. Y, U, and V signals are transmitted at the same time, which is parallel data, and the row field is output separately.
ITU-R (bt.656)8/10-bit data transmission; no need for synchronous signals; serial data transmission; 2 times the transmission rate of 601; first pass y, then pass UV. The synchronous signal of the row field is embedded in the data stream.

(2), mipi (Mobile Industry processor Interface)Is the abbreviation of mobileindustry processor interface mipi specification: Camera Workgroup: mipi camera Serial Interface 1.0 specification. Camera serial interface 2 V1.0 (CSI-2)

(3) AMX (Advanced extensible Interface)Is a bus protocol, which is the most important part of the AMBA (advanced microcontroller busarchitecture) 3.0 protocol proposed by arm, it is an on-chip Bus Oriented to high performance, high bandwidth, and low latency.

3. Interface Information

Fimc signal definition is as follows (YCbCr Mode)

Signal	I/O	Description	Type
Href	I	Synchronous Line Signal
Pclk	I	Pixel clock
Data [7:0]	I	Pixel data
Field	O	Field Signal
Mclk	O	System clock signal

 

The camera uses cam_mclk to provide a clock. The RST is a reset line, and the pwdn should always be low when the camera is working. Href indicates the line reference signal, pclk indicates the pixel clock, and vsync indicates the field synchronization signal. Once the camera provides a clock and resets the camera, the camera starts to work and transmits Digital Image Signals synchronously through href, pclk, and vsync. Data is transmitted through data0 ~ The eight data lines of data7 are concurrently sent.

4. Operation Sequence of different interface modes

ITU-R BT 656 input timing diagram, in which the synchronous signal has been embedded into the video data, so no additional line and frame synchronization signal is required.

ITU-R BT 601 input timing diagram, in which downlink and frame synchronization signals are independent of video data and therefore need to be synchronized.

(ITU-R BT 601: 16-bit data transmission; 21-core; y, U, V signal simultaneous transmission.
ITU-R BT 656: 9-core, do not need synchronous signal; 8-bit data transmission; Serial video transmission; transmission rate is 2 times of 601; first pass y, then pass UV .)

Synchronization signal delay parameters

Ø T1: indicates the insertion cycle before and after vsync.

Ø t2: indicates the insert period before href.

T3: indicates the href width.

T4: indicates the insert cycle after href

 

5. Camera clock domain, three clock types: system clock, pclk, and mclk

Each camera interface has three clock domains, each of which is a system bus clock, the second is the camera pixel clock pclk, and the third is the internal clock mclk. The system bus clock must be higher than pclk, And the cam_mclk must be fixed with Frequency Division, such as the PLL clock. If an external clock crystal oscillator exists, cam_mclk is empty. You do not need to synchronize the mmclk. pclk should be connected to the Schmitt-triggered level table.

6. hardware interface circuit

Interfaces on the master chip:

Camera Interface