ARM-based Linux Startup Analysis Report-arm + Linux Startup analysis (3)

(9) Call the decompress_kernel () function of the file Misc. C to decompress the kernel at the end of the cache.
(After the R2 address ). The register values are changed as follows:
R0 indicates the size of the extracted kernel.
R4 is the address when the kernel is executed
R5 is the start address of the kernel after decompression.
R6 is the CPU type value (processor ID)
R7 is the system type value (Architecture ID)
(10) after the reloc_start code is copied to the kernel (R5 + R0), the cache is cleared first.
Then run reloc_start.
(11) reloc_start reload the kernel starting with R5 at the R4 address.
(12) Clear the cache content, disable the cache, assign the architecture ID in R7 to R1, and execute
The kernel code starting with R4.
5) we will see this output at the beginning of kernel startup.
Uncompressing Linux... Done, booting the kernel.
This is also output by the decompress_kernel function, which calls the putc () Output string,
Putc is implemented in #/include/ASM-arm/arch-PXA/uncompress. h. Decompressed after execution
And then return to #/ARCH/ARM/boot/compressed/head. s to start the kernel:
Call_kernel: BL cache_clean_flush
BL cache_off
MoV r0, #0
MoV R1, R7 @ restore architecture number
MoV PC, R4 @ call Kernel
6) execute the zimage image to start_kernel ()
The startup of the entire ARM Linux kernel can be divided into three phases: the first phase mainly involves CPU and
System Structure Check, CPU initialization, and page table creation; the first stage of initialization is from
The entry (stext) ends before start_kernel. Code at this stage
In/ARCH/ARM/kernel/head. S. /ARCH/ARM/kernel/head. S is completed using assembly code,
Is the first file to be executed by the kernel. The main function of this assembly code is to check the CPU
ID, architecture number, initialize the page table, CPU, BBS, and other operations, and jump
Start_kernel function. Before execution, the processor status should meet:
R 0-shoshould be 0
R1-unique architecture number
MMU-off
I-Cache-on or off
D-Cache-off
A) Flowchart

B) code comments
#/ARCH/ARM/kernel/head. s
/*
* Swapper_pg_dir is the virtual address of the initial page table.
* We place the page tables 16 K below kernel_ram_vaddr. Therefore, we
* Must make sure that kernel_ram_vaddr is correctly set. Currently,
We * perform CT the least significant 16 bits to be 0x8000, But we cowould
Probably relax this * restriction to kernel_ram_vaddr> = page_offset +
0X4000.
*/
# If (kernel_ram_vaddr & 0 xFFFF )! = 0x8000
# Error kernel_ram_vaddr must start at 0xxxxx8000
# Endif
. Globl swapper_pg_dir
. Equ swapper_pg_dir, kernel_ram_vaddr-0X4000
. Macro pgtbl, RD
LDR/RD, = (kernel_ram_paddr-0X4000)
. Endm
/*
* Since the page table is closely related to the kernel start
Address, we
* Can convert the page table base address to the base address of
Section
* Containing both.
*/
. Macro krnladr, RD, pgtable, rambase
BIC/RD,/pgtable, #0x000ff000
. Endm
/*
/*
* Kernel startup entry point.
*---------------------------
*
* This is normally called from the decompressor code.
Requirements
* Are: MMU = OFF, D-Cache = off, I-Cache = dont care, R0 = 0,
* R1 = machine NR, R2 = atags pointer.
*
* See Linux/ARCH/ARM/tools/Mach-types for the complete list
Machine
* Numbers for R1.
*/
. Section ". Text. Head", "ax"
. Type stext, % Function
Entry (stext) // kernel entry point
MSR cpsr_c, # psr_f_bit | psr_ I _bit | svc_mode
// Program status. Disable FIQ and IRQ and set the supervisor mode. 0b11010011
MRC P15, 0, R9, C0, C0 @ get processor ID
BL _ lookup_processor_type @ R5 = procinfo R9 = Cupid // jump
Judgment
// CPU type. Check whether the ID of the running CPU is consistent with the ID supported by the Linux compilation.
And so on
Movs R10, R5 @ invalid processor (R5 = 0 )?
Beq _ error_p @ Yes, error 'P'
BL _ lookup_machine_type @ R5 = machinfo
// Jump to the system type to check whether the architecture number value of the R1 register is supported.
Movs R8, R5 @ invalid machine (R5 = 0 )?
Beq _ error_a @ Yes, error 'A'
BL _ vet_atags
BL _ create_page_tables // create a core page table
/*
* The following cils cpu specific code in a position independent
* Manner. See ARCH/ARM/MM/proc-*. s for details. R10 = base
* Xxx_proc_info structure selected by _ lookup_machine_type
* Above. on return, the CPU will be ready for the MMU to be
* Turned on, and R0 will hold the CPU control register value.
*/
LDR R13, _ switch_data @ address to jump to after
@ MMU has been enabled
Adr lr, _ enable_mmu @ return (PIC) Address // LR = 0xc0028054
Add PC, R10, # procinfo_initfunc
@ Initialise processor // R10: pointer to processor
Structure
#/ARCH/ARM/kernel/head-common.S
*/
# Define atag_core 0x54410001
# Define atag_core_size (2*4 + 3*4)> 2)
. Type _ switch_data, % object
_ Switch_data:
. Long _ mmap_switched
. Long _ data_loc @ r4
. Long _ data_start @ R5
. Long _ bss_start @ R6