Complement the base shell and makefile

Shell Description: The command line of the operating system terminal

The shell can be understood as a command-line interface that the software system provides to the user for operation. A way of human-computer interaction

We can use the shell to interact with software systems such as the operating system and uboot.

Shell script running mechanism: explain the running

After the shell is written with the source code, the source code can run directly, unlike the C to compile the link.

Shell scripts in the program is interpreted to run, meaning that our source code is written, at run time, our Shell parser will be one line of the shell to explain the source code, and run line by row, is the line-by-row interpretation of the run.

That is, the Shell scripting language is not like our C language, after writing the source code, to compile the link into a binary executable program, finished running

Scripting language is after we write good source code, to run this script, that is, when running the source code, the line of our script to the source code to the binary program to run to our CPU.

Write a Shell yourself

1, our shell is running directly under Linux, unlike the C language, can be written under Windows, after the end of the Linux GCC compiler processed, will be directly into the binary program to run, our shell directly under Linux directly run , written well, runs directly, so if we write the shell in Windows, it is not possible to run it directly under Linux, because in Linux, the line break ' \

n ', and the line break in Windows is ' \ r \ n '. So we can't write this shell in the editor under Windows and write it in the editor under Linux.

2, Shell program running method:

More commonly used, the first kind:./xx.sh and we run executable programs very much like, but this method to run, requires that the shell program must have the ability to run.

The second type: source xx.sh source is a command under Linux that executes a script command, so that you do not need our shell scripts need to have executable permissions

The third: Bash xx.sh bash is a shell interpreter, which is equivalent to bash as an executable program under Linux, which directly interprets the run. sh file

3. Write a Hello Word

The first line of #!/bin/sh means that we have this script file, in the future from the beginning of the #!, with the SH program under the/bin execution.

Echo is a command under Linux that means printing.

4, shell script is actually a command line under the input (type of command), written into the shell into the shell of the program, the execution of the shell to do. So the shell is to facilitate us, we can do not have to manually input under the command line, many times to repeat things, you can directly through the shell to simplify our operation.

The shell is a weakly typed language, that is, the definition of a variable has no explicit type, and in the shell, the variable has no type.

So in the shell,

The definition of a variable is no type and can be initialized, such as defining a variable string and initializing it, string= "Hello word" is defining a string variable and initializing it to Hello Word. There can be no spaces on either side of an equal-value assignment in the shell.

The assignment of a variable is the same as the value assigned to C.

The reference to the variable is to be quoted with the $ symbol. The $ symbol is the reference symbol for the variable.

Note: When using the $ symbol, the string after the $ symbol is parsed into a variable and parsed, and if the subsequent string is undefined, then parsing the variable that has no definition and assignment will be resolved to a variable with an empty value, and the reference will be empty.

In the shell, strings can be used without double quotes, but if the flaw without double quotes is, you cannot output "or escape characters."

Adding single quotes is literally all output, not replaced.

Double quotation marks, if there is a transfer character (\ "\$) in the double quotation mark, and so on, the escape character is escaped to the" $ symbol "in the output content.

The inverse quotation marks, the resulting part represents the command in Linux, when we assign a value to a variable, sometimes the value that we want to assign to the variable is the return value of executing the Linux command.

such as: pwd= ' pwd ', double quotes can contain the mypath= "' pwd ' \include" assigns the current absolute path to MyPath

The If judgment structure in the shell

A typical if-statement format that we can use

if [expression]; Then

Xxx

Else

Xxx

Fi

This is the format, in fact, and C is almost,; Then is the fixed-format fi is the IF's closing

1, determine whether a file A.txt exists,-f

If [-F a.txt]-F is to determine whether a file exists, the existence is established.

2. Determine if a directory exists,-D

3. Determine if the strings are equal "str1" = "str2"

4. Determine if the number is equal (-EQ), greater than (-GT), less than (-LT), greater than or equal to (-ge), less than or equal to (-le)

5. Determine if the string is empty (-Z

6. The If statement uses-O to represent logic or

7. Logic && and logic or | | In the shell, you can abbreviate the If judgment

[-Z $str] | | echo "Yes" means shorthand for if, if Str is empty, it will not execute logic or | | The subsequent statement, if STR is not empty, is not true, then the logic is executed or | | The following statement. The logic in the C language or | | , as if the | | Logical symbol in front of the set up, then do not perform | | The back, if | | If the previous is not established then the execution | | Behind the

[-F A.txt] && touch b.txt If a.txt file exists, create no B.txt

Loop structure in the shell:

For loop format

For I in 1 2 3 4 5 xxx (something in the back can be a number, a character)

Do

Echo $i

Done

While loop format prints 1 to 10

I=1

j=11

While [$i-lt $j]; Do

Echo $i

i=$ (($i + 1))

Done

Echo creates a file and appends the input file

>xx.txt Create a file Xx.txt

>>xxx.txt in this file xxx.txt, append content

echo "Text" > A.txt Create a file a.txt, and enter text into A.txt

echo "Zhuijia" >> a.txt add Zhuijia content to the A.txt file.

Calling the shell program's arguments

$ #表示调用shell程序时, number of arguments to the shell

$, $, $, $ ... each parameter of the argument is represented in turn

In C, we argc is the number of arguments, and the number of these arguments includes./a.out

In the shell, we $ #表示给shell传递的参数个数, but this number does not include the source loop.sh

In the C language, the parameters in our argv[0] represent the./a.out argv[1] parameter, which is the argument behind/a.out, and so on.

In the shell, we are saying that we execute the name of our Shell's parsing executable program.

$ $ represents our first valid parameter, and so on

$# in the shell, such as the built-in variables, not only can we pass the different parameters to change, can also be changed by the shift command, the shift can let us parameter $ $ $ $, and so on, left one, so that $ #的值少一, the original value was removed, now the $ The value of 2 becomes the original value.

Second, Makefile

Goals, dependencies, commands

The goal is what we end up generating.

Dependency is the raw material used to generate the target

The command is the processing method

So the make process is the process of making our dependence on processing the target.

Wildcard% and makefile Auto derivation (rule)

% is a wildcard in makefile, meaning that it represents one or more characters, and%.O means all of the. o Files

We make XXX (our goal) or the rules of the make,makefile began, first will see the target of dependence, existence does not exist, if not exist will be the target of this dependence to find this dependence, If this dependent dependency is found, the dependent command will be executed, and the dependent dependency can be processed into a dependent target, then the initial target can find the dependency, and the dependency will be processed into a target by command.

Like LED.BIN:LED.O.

Command

%.O:%. S

Command

The above Led.bin is the goal of our make, LED.O is the first goal of the dependence, the results in the current directory can not find this dependency, and will be the target of this dependency,%.O to become the target of this dependence, this goal to see his dependence exists not exist, Find in the current directory. s end of the file, it will execute this dependent command, the dependent command into the. o file, so that our led.bin this goal to find his dependence, you can execute the command, will led.o this dependence processing into led.bin this goal

Defining variables and using variables in makefile

Variables are defined in makefile, variables are used, and our shell scripts are of type, because variables are not types, and references to variables are also referenced by $.

Pseudo-Target (. Phony)

Pseudo-goal means that I do not generate this goal, this goal is not a file or other things, but we want to execute the command under this goal, the pseudo-target is not dependent, because I just want to execute this pseudo-target command, makefile, clean is a pseudo-target.

In order to declare that this goal is a pseudo target, let others know it at a glance, so it is usually used. Phony to declare these pseudo-targets, such as:

. Phony clean(declares that clean is a pseudo-target)

Clean

RM *.o *.elf *.bin

Reference makefile (include directive) in Makefile

Because when the project is very large, it may be necessary to write a few makefile, so we need to refer to the other makefile in the makefile of the Lord, the reference method is to use the directive of include, this instruction is to expand in place meaning, with our C language of the # Include tasks in the pre-processing phase, expanding the contents in place

Supplemental Learning for Makefile:

1, makefile in the note with #

2. The @ at the front of the command is used for silent execution

The @ at the front of the makefile command line indicates a silent execution

What do you mean, makefile? By default, when Makefile executes a command, it prints out the command first and then executes the command after it is finished. If you do not want to see this line of command, go directly to execute this command, you can add @ in front of this line of command, silent execution can be

3. Several variable assignment operators in makefile

(1) = means that if the previous variable is not assigned a value, the assignment is performed

(2) + = means to give a variable that has been assigned to the value of the continuation assignment

(3) = simplest assignment

(4): = Assignment is also generally the case

The above two, in most cases, are the same. But in some cases it's not the same.

= In the assignment of a variable, when I parse this variable, the value of the parsed variable is the last time with the = number assigned to the value of the variable, not to say that the value of the variable is parsed, it must be the value of the above = assigned value, to look back to see if there is a = number to assign the variable again, If there is any later, even if the variable is parsed before, the parsed value will be the value of the following

: = When you assign a variable and parse it, it is the value of the value assigned before the variable, regardless of the value assigned to the variable.

When we parse a variable, we look at the value of the variable being assigned: = or = if it is used: = then the value of the last assignment of the variable is looked forward, and if it is = It will be looked back at the value of the last assignment of the variable

Environment variables in the makefile

The environment variable in makefile is the common variable exported with export, the general environment variable is capitalized in Makefile, and the normal variable is lowercase.

The difference between the environment variable and the ordinary variable in makefile, in makefile, the environment variable is exported by export is called environment variable, it is can be the whole project makefile shared variables, and ordinary variables are only in the current makefile can be used.

Some of the environment variables in makefile are the environment variables we pass in the execution environment, and we can take the parameters when make

Make CC=ARM-LINUX-GCC This allows the value of the CC variable in makefile to be the value of the parameter given to us at this time.

Supplementary study of Makefile 2:

Using wildcard characters in a makefile

* any of the characters

? a character

[] the contents of which are sequentially matched to the outside of us.

% also represents any character, except that% is used only in the rule description, so it is called a regular wildcard

%.O:%. S This is the rule description

Arm-linux-gcc-o [email protected] $<-c-nostdlib

Automatic variables in the makefile

Commonly used automatic variables

[Email protected] The target file name that represents the rule

$> Dependent file name for the rule

$^ Dependent collection of files

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Complement the base shell and makefile