Computer components-Communication between parts. Bus buses

• What does the bus do? Plainly, it is used to transfer data between parts of the computer. For example, my main memory stored in the data CPU to use, need a line to pass it, the CPU internal registers between, register and Alu, CU and various parts and so on, and so on many places, in short, the parts need to transfer data
• The transmitted data is divided into three kinds, corresponding to three kinds of functions of the bus
  
  • Data bus
  • Address bus
  • Control bus
• So why is it called the "total" line? That's because in most cases, we can't connect any two parts, because the number of parts is too much.
  
  • So we only use a bus to transmit, then the first question is, how to distinguish between data, address, control these three categories??
  • It is true that there is a technique called bus multiplexing for data and addresses, because the computer works under the control of time series, so that the data on a bus is defined as "data" or "address" in different periods. For the control signal has not yet done this,,,
  • Let's just split three buses.
  • Then there is a problem, only three lines, although it can be distinguished whether the data or the address or control signal, but for many parts, how does it know that the current bus transmission of data is not to it? Because a data line is connected to all the parts, a to B sends the data when the above data is given to B, for the other parts is useless, the wrong data.
  • So, you need to control the signal to control it. A when sending data, the control signal only allows B to receive data from the data bus, and the other parts are not received.
• Suddenly think of a metaphor, just to explain how the bus works, not the historical development
  
  • The bus is probably like a water pipe, and the waterworks has no way of laying out a special conduit for all the families, so it only lays a pipe to connect all the families. Each family has its own family work to contribute to the community, which needs to use water, you can open the water pipe at any time to pick up.
  • Later, the waterworks bought the gas station, but did not want to lay more lines, so they still use a pipe, but tell all the family, only when you receive the signal from the tap water, from the pipeline to take out the running water you need, received a petrol signal, take out is gasoline. The transmission of the signal also requires a line, so a wire is laid to transmit the signal.
  • It turns out that this is sensible, because the water-supply plants are getting more and more developed, gradually buying edible oil plants, gas plants, salt plants, hamburger factories and so on, but still using a pipe can serve all the family, but need to transmit more control signals, which is more than laying a pipeline to save more money
  • Later found that the exchange between families is also more frequent, since there is such a convenient total pipeline why not? So everyone was under control of the signal, and the family who was told to put things on the pipe was able to put things on the pipe and then inform who to pick up the stuff. These pipes become two-way traffic, which can be taken or put.
• So a very important feature of the bus is that it is shared with the parts that are hanging on it.
  
  • If there is a privately traded agreement between the two families, or if a family and a waterworks have a relationship that allows a person to drive something specifically, it is equivalent to a dedicated communication channel, not a bus
• corresponding to the computer, the bus is "sharing a group of electric conductors in a single time" to achieve.
• Too much nonsense ...

Bus composition and characteristic composition

• Transmission lines, interfaces, and bus controllers
  
  • In addition to the information lines that transmit data, addresses, and control signals, there are also power and grounding cables to connect to each part, and there may be alternate lines to prevent bus failures
  • The interface consists of a three-state gate and a buffer register. Three-state gate can determine the current bus and this part of the Unicom state, the output of the three-state gate can be 1, 0 and high impedance of three states, more than one EO enable to control
  • Because of the bus sharing, a bus controller is required to control the use and distribution of the bus,

Characteristics

Functional characteristics

• Transmission line Classification by function (what data is transmitted)
  
  • Address bus
  • Data bus
  • Control bus

Electrical characteristics

• That's the transmission direction.
  
  • One-way bus: Data can only be transferred in one direction. Address line one-way is enough =, =
  • Bidirectional bus: Full-duplex and half-duplex
    
    • Full Duplex: Data can be transmitted in both directions
    • Half-duplex: data can only be transferred in one direction at a time
• Don't ask me how I realized it, I don't know. I guess it's,,,,,, in the digital circuit class that I want to learn.

Time characteristics

• According to the timing, the signal on each transmission line is valid at what time.
  
  • Not reading the data within the specified time, presumably (yes, I guess), or I can't read it or read it wrong.

Bus design and implementation

• Speaking of which is only a single bus structure, that is, all the modules share a bus.
  
  • But
  • A bus access to the module is limited, too many modules will make the bus load too high, reduce communication efficiency
  • The operating frequency of each module can also be seen as a different speed, such as the CPU is significantly faster than the I/O interface, so when the slow-working module occupies the bus, the work of the module is finished to use the bus, but the bus is occupied by the slow module has to wait.
• So there's a multi-bus structure with local bus
  
• However, the frequency of work between the components is not the same, it is difficult to coordinate, the result is reduced efficiency, so there is a hierarchical bus structure, to deal with the coordination between the components
  
• There is further
  
  • Hierarchical bus structure with local bus
  • Multi-bus structure connected using a bridge
  • Multi-bus architecture with stronger fault tolerance

Bus control

• There are two good words to summarize the two characteristics of the bus

  • The mutex of a transmission: Only one feature is allowed to send data to the bus at a time
  • Accepted sharing: Allows multiple features to receive information transmitted on the bus at the same time

• So how to coordinate the relationship between multiple parts of this information transfer, you need someone to stand up to control the use of the bus

• Analysis based on two properties
  
  • How to decide a moment from the function to send data to the bus, called this part of the main part, the main part of the bus control. This section is called "bus Quorum".
  • How should I control when I receive the information? What if I had to receive the data and the main part didn't put the data on the bus? What if I'm going to take the main part and undo the data from the bus? This part is the communication control of the bus.

Bus quorum

• If it is unfortunate that only one person stands out to control the bus, then that is the centralized bus quorum , who comes to be the main part i.e. who comes to occupy the bus by his "centralized" control

  • Serial link mode: All components send a "bus request" signal to the bus arbiter via a line.
    
    • If the component Y sends the bus request signal, just as the bus is idle, then the bus arbiter sends out a bus-usable signal, which, if it receives it, consumes the bus, and it also sends the bus busy signal to tell the other parts that the bus is not idle.
    • However, the transmission of the bus available signal is passed down from part 0 in turn, and if part 0 does not make a bus request, the bus available signal is passed to the next part 1. This is normal, who let the bus available signal to pass me first? Even if the part behind you is requesting the bus, it is also the part of the request bus in front of me to receive the signal that the bus is available first.
    • This creates a default priority, and because it is in series, once a component is broken, the component behind it will never receive the bus available signal
    • There is a name called "Daisy Chain" ... This must have been the name of a long time ago.
  • Timing Query method: Based on serial chain mode
    
    • For all part numbers, when the bus request is first received, the counter is counted from 0, and the value of the counter is periodically broadcast to each part as a signal available on the bus
    • This value corresponds to the number of parts that can be used to receive the available signal from this bus, so after broadcasting, all the parts receive the bus available values, compare their numbers if the bus busy signal to occupy the bus, once received the bus busy signal, the counter will stop counting (instead of 0, The serial link corresponds to the counter 0).
    • Otherwise the counter will be + 1, then the next time the bus is available, the components that can respond to the bus's available signal are next.
    • Moreover, the value of the counter can be controlled by software, which also means that the priority can be changed at any time by the software.
    • Significantly more complex, more expensive lines, and due to the need to pre-numbering, the number of lines depends on the number of bus components, etc., making scalability poor. In addition, the frequency of the timing signal depends on the operating frequency of the counter, so it is not very high.
  • Independent request Mode
    
    • As opposed to serial wiring, the independent request is the bus request and the bus available line for each part has a dedicated to the bus arbiter, bus busy signal only need one root is enough
    • Each part sends a bus request signal to the bus arbitrator independently, and if the current bus is idle (the bus is busy without a signal), then the bus arbitrator sends a bus-available signal to the part, and for multiple simultaneous bus request signals, the bus arbitrator internally implements the quorum algorithm based on the hardware to determine who can occupy the bus
    • The quorum algorithm has a predetermined (static priority), an adaptive (Dynamic priority), a cyclic count (equality), a first-come-first service (queue).
    • It's very flexible, but the cost is the most expensive,,, look at that root line, it's all money.
  • Fixed time slice mode
    
    • Using the idea of time-sharing
    • Each component is then used by a fixed-length time slice in turn to use the bus, even if the current part does not have a bus, it will have to wait until the current time slice has passed before changing to the next part.
    • The simplest, fairest, lowest cost, least effective (but in some cases enough)

• It's distributed outside the concentration.

  • Distribution means you don't need a big brother to take the lead to pronounce, but everyone together according to the rules to discuss who occupy the bus. There is no longer a single arbiter, but an arbitrator with multiple distributions.
  • The bus standard for multi-processor-based computer systems employs a distributed bus arbiter, which means that this distribution is typically used to coordinate multiple processors
  • But parts of the work thou mayest or working, rather than busy to discuss this kind of thing, so to a proxy "distributed bus arbiter", each agent hand in the priority of their own components, agents are not allowed to discuss it.
  • Bootstrap Distribution
    
    • Bootstrap does not mean equality, which means a fixed priority, but requires you to detect there is no higher priority than you in the use of the bus
    • A component, first detect the bus busy whether there is a signal, if there is a wait, otherwise it is higher than the priority of the components of the bus request signal has (that is, if more than one part of the bus request signal, bus busy or no signal state, but always can not be assigned to multiple parts using the bus bar), if there is, wait, Otherwise use the bus and continue to issue the bus busy signal
    • Device I sends a bus request signal via a BRi line, and the BR3 line of the lowest priority device 3 is treated as a bus busy signal
      
      • Wait, listen to my analysis.
      • Initially no devices are using the bus, so the Br0-br3 are free
      • Equipment 3 To use the bus, first detect the bus busy (BR3) there is no signal (no), and then detect BR0-BR2 there is no signal (no), so the device 3 to BR3 sent a bus request signal, and continue to send signal to BR3 as the bus busy signal
      • Devices 1 and 2 also use the bus, but the bus busy (BR3) is a signal, so to wait (that is, the device 3, although the lowest priority, but also have to respect it, when using the bus can not be interrupted), so device 1 and device 2 maintain the bus request signal, that is BR1 and B R2 are in a signal state.
      • Equipment 3 ran out, withdrew the signal of the BR3, at this time equipment 1 and Equipment 2 detected BR3 No signal, the bus is not busy, but the device 2 detects a signal on the BR1, means there is 2 more priority than the device 1 in the request bus, so equipment 1 occupy the bus, and send a letter to BR3 device 1 can remove the BR1 request signal.
    • That is, BR3 is both the bus request line for device 3 (lowest priority) and the bus busy line for everyone. Because the lowest priority device does not need to be based on the bus request signal to determine whether there is a higher priority, and only need to be based on the bus busy signal. The bus request signal sent by the lowest priority device, if it works, is only available when the bus is not busy. So the bus request and bus busy for the lowest-priority device can be combined.
    • A root line is money Ah, is the cost ah, is the complexity of ah, these things can be less
    • At this time, the distributed bus arbiter is relatively simple, only need to detect the corresponding line (bus busy and higher priority bus request) there is no signal on it, so built into the device is not not possible, so that you do not have to set up a bus arbiter alone.
  • Parallel Competition
    
    • Ha, this is more complicated, the equipment itself is uncertain, so need a distributed bus arbiter
    • A component first sends a "priority ap#" code to its corresponding distribution arbiter (the M-bit binary can represent 2^m priority)
    • Distribution arbitrator publishes its own ap# to the total "request/quasi-use" line
    • All ap# do logic or arithmetic on the "request/quasi-use" line
    • Each distribution arbiter then reads the results on the "request/quasi-use" line, and if the result is greater than its own ap#, then a higher-level device is requested, so it temporarily revokes its ap#
    • With the passage of time, the "request/quasi-use" line left the highest priority ap#, then this time its distribution arbiter again read, and their own ap# the same, there is no higher than their own, so can occupy the bus and issued a bus busy
  • Conflict Detection
    
    • This is easy.
      
      • If the bus is busy, wait for
      • If the bus is not busy
        
        • If you only request (no conflict), use the bus
        • If you are not alone in the request (there is a conflict), all conflicting requests (that is, yourself and other requests) are postponed a random time to request
    • Sorry, no picture.

Communication control

Communication requires the cooperation of sender and receiver, sending data called "source part", accepting data called "Destination part"

• Synchronous Communication
  
  • is based on the control of the timing
    
    • Source part sends data and keeps the signal at a fixed time, and does not confirm whether the destination part received data
    • purpose part reads at a fixed time Regardless of whether you can read the data (there is no data on the bus), or whether the read data is correct (read the data sent by the source part or other messy data) where is the
  • timing? Can be controlled by the central time, or each part comes with the time label, but need to synchronize with the central time mark, like our mobile phone, computer time, each time the network will be opened on the network and standard time synchronization
  • such as 8086 microprocessor using synchronous communication reading memory data when
  • 
    
    • t1cpu send a memory address
    • T2CPU send read signal
    • T3 main memory put the data up
    • t4cpu read Data
• Asynchronous communication
  
  • Is the need to confirm the operation between the two sides, this confirmation is achieved through the "Handshake" protocol, a variety of but roughly divided into unilateral control and bilateral control
  • Single-sided control
    
    • Again, the purpose of the component control or the Source component control
    • Purpose control
    • 
      
      • The destination part sends the data request first, after the delay of the T time arrives the source part, the source part puts the data to the bus, passes the T time Delay data arrives the destination part
    • Figure
      
      • The source part sends the data first, T1 time sends the data ready signal again (prevents the data ready signal to arrive the destination part earlier than the data), the destination part receives the data ready signal to read the data on the bus. Two data send interval T2 time, this short time to complete the source part to the data buffer load data, bus arbitration logic complete arbitration.
  • Bilateral control
    
    • Both sides are involved in the confirmation, but still sub-primary and secondary, and further divided into "non-interlocking", "semi-interlocking", "full interlock"
    • The book is only about the source parts mainly ... I didn't check any more information ...
    • Just look at the picture. It should be easy to read.
• Semi-synchronous communication
  
  • The two extremes have obvious advantages, but the drawbacks are obvious.
  • People like to combine several extreme ways to achieve a better balance.
  • The macro-based synchronous communication to organize, local to use asynchronous response way

Bus performance evaluation

• Bit width
  
  • The number of bits of data that the bus transmits at one time, that is, the number of lines of the bus, a line can only wear 1 bits (I guess there is electricity on the line or no power.) No electricity actually says it's not over, because I've always seen "high" or "low". ）
• Operating Clock frequency
  
  • That is, the frequency of the control bus clock signal, the unit is generally Hz, that is, how many beats a second is divided into
  • KHZ = 1000HZ
  • MHZ = 1000KHZ
  • ......
• Transmission cycle of single data
  
  • The way of data transmission is divided into normal transmission and burst transmission.
  • Normal transmission
    
    • Send an address first, then send a data
  • Burst transmission
    
    • Send one address as the first address and then multiple data
  • A clock cycle is the length of a beat
• Load capacity
  
  • The maximum number of parts that can be hung on the bus, in fact, is not too large, too large at the time of the arbitration will have a relatively long delay, and the bus itself is not load
• Data transfer Rate
  
  • The number of bytes that the bus can reliably transmit data in one second
  • Units are kb/s, MB/s
  • The maximum data transfer rate is also known as bandwidth
  • Bus bandwidth = Bus bit width * bus operating frequency/8

Computer components-Communication between parts. Bus buses