Computer Register Classification

Computer Register Classification Introduction: 32-bit CPUs contain four data registers (eax, EBX, ECx, and EDX), two address changes and pointer registers (ESI and EDI) 2 pointer registers (ESP and EBP) 6 segment registers (ES, Cs, SS, DS, FS, and GS) 1 Instruction Pointer register (EIP) 1 sign register (eflags) 1. The data register is mainly used to save information such as the operands and operation results, thus saving the time required to read the operands to occupy the bus and access the memory. The 32-bit CPU has four 32-bit General registers eax, EBX, ECx, and EDX. Access to low 16-bit data does not affect high 16-bit data. These 16-bit low registers are named ax, BX, CX, and DX respectively, which are consistent with the registers in the previous CPU. 4 16-bit registers can be divided into 8 independent 8-bit registers (ax: Ah-Al, Bx: bh-BL, CX: ch-cl, DX: DH-DL ), each register has its own name and can be accessed independently. Programmers can flexibly process the word/byte information by taking advantage of the "severable" feature of data registers.
The register eax is generally called an accumulator. operations performed with the accumulators may take less time. It can be used for multiplication, division, input/output, and other operations. It is frequently used. The register EBX is called base register ). It can be used as a memory pointer; register ECx is called count register ). During loop and string operations, use it to control the number of loops. during in-place operations, use Cl to specify the number of shifts when multiple bits are moved; register edX is called a data register ). During multiplication and division operations, it can be used as the default operand for calculation, or it can be used to store the port address of I/O.
In a 16-bit CPU, ax, BX, CX, and DX cannot be used as the base address and address change register to store the address of the storage unit. In a 32-bit CPU, its 32-bit registers, eax, EBX, ECx, and EDX, can not only transmit data, temporarily store data to save Arithmetic Logic calculation results, but also serve as a pointer register, these 32-bit registers are more universal. 2. The address change register 32-bit CPU has two 32-bit General registers ESI and EDI. Its Low 16 bits correspond to the Si and Di in the previous CPU, and its access to low 16 bits of data does not affect the high 16 bits of data. Registers ESI, EDI, Si, and Di are called index register. They are mainly used to store the offsets of storage units in segments. They can be used to address multiple memory operands, it is convenient to access the storage unit in different addresses. The address change register cannot be divided into eight-bit registers. As a general-purpose register, you can also store the operands and results of arithmetic logic operations. They can be used as general memory pointers. In the execution of string operation commands, they have specific requirements and special features. 3. The low 16-bit pointer register corresponds to the BP and SP in the previous CPU, and the access to the low 16-bit data does not affect the high 16-bit data. The 32-bit CPU has two 32-bit General registers, EBP and ESP. They are mainly used to access the storage units in the stack and stipulate that EBP is the base pointer (
Pointer) registers, which can be used to directly access the data in the stack; esp is the stack pointer register, which can only access the top of the stack. Registers EBP, ESP, BP, and SP are known as pointer register. They are mainly used to store the offset of storage units in the stack. They can be used to address multiple storage operations, it is convenient to access the storage unit in different addresses. Pointer registers cannot be divided into eight-bit registers. As a general-purpose register, you can also store the operands and results of arithmetic logic operations. 4. segment register is set based on the memory segment management mode. The physical address of a memory unit is composed of the block register value and an offset, so that two smaller-digit values can be combined into a memory address that can access a larger physical space. Segment register inside the CPU: ECS -- segment register (Code
Segment register), whose value is the segment value of the code segment; eds -- data segment register (data segment register), whose value is the segment value of the data segment; ees -- extra segment register; its value is the segment value of the additional data segment; Ess -- stack segment register; its value is the segment value of the stack segment; EFS -- extra segment register; EGS -- extra segment register.
In a 16-bit CPU system, there are only four segments of registers. Therefore, the program can directly access up to four segments in use at any time. In a 32-bit microcomputer system, it has six segment registers. Therefore, a program developed in this environment can access up to six segments at the same time. The 32-bit CPU has two different ways of working: real-time mode and protection mode. In each mode, segment registers have different functions. The rules are described as follows: the implementation method: CS, DS, es, and SS of the first four segment registers have exactly the same meaning as those of the segment registers of the previous CPU, the Logical Address of the memory unit is still in the format of "segment value: Offset. To access data in a memory segment, the offset between the register and the storage unit must be used. Protection Mode: In this mode, the situation is much more complicated. The Block Value loaded into the segment register is not a segment value, but a value called "selector ..
5. The 32-bit CPU of the instruction pointer extends the instruction pointer to 32-bit and records it as an EIP. The 16-bit low EIP address serves the same purpose as the IP address in the previous CPU. The EIP and instruction pointer are the offsets of the commands to be executed next time in the code segment. In a system with the prefetch command function, the command to be executed next time is usually prefetch into the command queue unless the transfer occurs. Therefore, the command queue is not considered when you understand their functions. 6. Mark register 1. Operation Result flag 1. Carry mark CF (carry flag) carry mark CF is mainly used to indicate whether the operation generates carry or borrow digits. If the highest bit of the calculation result produces a carry or borrow digit, the value is 1; otherwise, the value is 0. This flag is used for addition and subtraction of the number of characters (in bytes), comparison of the number of unsigned values, and shift between words (in bytes, commands that specifically change the CF value. 2. Parity mark PF (parity
Flag) the parity mark PF is used to reflect the parity of the number of "1" in the calculation result. If the number of "1" is an even number, the PF value is 1; otherwise, the value is 0. PF can be used for parity check or to generate parity bits. In the process of data transmission, in order to provide the reliability of transmission, if the parity method is adopted, this flag can be used. 3. When the secondary carry flag is AF (Auxiliary carry flag), the value of the secondary carry flag is set to 1; otherwise, the value is 0: (1) during word operations, when low bytes are carried to the high byte or borrow; (2) when the byte operation occurs, when the low 4 bits are carried to the high 4 bits or borrow bits. For the above 6 operation result flags, in general programming, flags CF, ZF, SF, and of are frequently used, the use frequency of flag pF and AF is low. 4. Zero sign ZF (zero
Flag) The zero sign ZF is used to indicate whether the calculation result is 0. If the calculation result is 0, the value is 1; otherwise, the value is 0. You can use this flag when determining whether the calculation result is 0. 5. Sign sign SF (sign flag) Sign SF is used to reflect the sign bit of the calculation result. It is the same as the highest bit of the calculation result. In a microcomputer system, the number of symbols adopts the code representation. Therefore, SF also reflects the positive and negative numbers of the calculation results. When the calculation result is a positive number, the value of SF is 0; otherwise, the value is 1. 6. Overflow sign of (overflow flag) overflow sign of is used to reflect whether the result of the addition or subtraction operation of the number of symbols overflows. If the calculation result exceeds the range expressed by the current number of BITs, it is called overflow. The value of is set to 1. Otherwise, the value of is cleared to 0. "Overflow" and "carry" are two different meanings. Do not confuse them. For details, refer to the relevant chapter in the computer composition principles course. 2. Status Control flag the status control flag is used to control CPU operations. They must use special commands to make changes. 1. Tracking mark TF (trap
Flag) when the trace flag TF is set to 1, the CPU enters the single-step execution mode, that is, each execution of a command generates a single-step interruption request. This method is mainly used for program debugging. There are no special commands in the command system to change the TF value of the flag, but the programmer can use other methods to change its value. 2. The if (Interrupt-enable flag) interrupt flag is used to determine whether the CPU responds to the interrupt request sent by the external WAF instance. However, no matter what the value of this sign is, the CPU must respond to the interrupt requests from the outside of the CPU that cannot be blocked and the interrupt requests generated inside the CPU. The specific provisions are as follows: (1) When if = 1, the CPU can respond to the interrupt requests that can be blocked outside the CPU; (2) When if = 0, the CPU does not respond to the interrupt requests that can be blocked outside the CPU. The CPU command system also has special commands to change the if value of the flag. 3. direction sign DF (Direction
Flag) Direction Flag DF is used to determine the direction in which the pointer register is adjusted when the string operation command is executed. Specific provisions are provided in section 5.2.11-string operation instructions. In the microcomputer instruction system, special commands are also provided to change the value of the Flag DF. Iii. 32-Bit Flag register added flag 1. I/O privileged flag iopl (I/O privilege level) I/O privileged flag is represented by two binary bits, it is also called an I/O privileged field. This field specifies the privileged level required to execute the I/O command. If the current privileged level is less than or equal to the iopl value, the I/O command can be executed. Otherwise, a protection exception occurs. 2. nested task flag NT (nested
Task) nested task flag NT is used to control the iret execution of the interrupt return command. The specific provisions are as follows: (1) When Nt = 0, use the stored values in the stack to restore eflags, Cs, and EIP, and perform regular interrupt return operations; (2) when Nt = 1, the return is interrupted through task conversion. 3. the restart flag is used to control whether debugging fault is accepted. NOTE: If RF is set to 0, the debugging fault is "accepted"; otherwise, the fault is rejected. After successfully executing a command, the processor sets the RF to 0. When a non-debugging fault is received, the processor sets it to 1. 4. Virtual 8086 mode: VM (Virtual 8086 mode). If the value of this flag is 1, the processor is in the virtual 8086 mode. Otherwise, the processor is in normal protection mode.