Computer operating System (II)---processor Architecture (iii) (RPM)

the article part picture text comes from the reference article, the reference article summarizes very well.

Instruction processing phase

To reduce the complexity of the implementation, a unified framework is used to share parts. We organize the Y86 instruction processing into the following stages:

• Fetch: Reads the instruction from the instruction register.
• Decode (Decode): reads the program register.
• Execute (EXECUTE): The ALU calculates the result (there are two kinds of calculated values (for updating program registers) and one is a valid address for calculating memory references).
• (memory): read-write memory.
• Writeback (write back): writes back to the register file.
• Update PC (PC Update): Sets the PC to the address of the next instruction.

First, you just need to know the stage of the execution of an instruction, and then analyze the execution process of Y86 's specific instructions.

Two points to be aware of:

1. Under the unified framework, each instruction will undergo all of the above phases.

2. In seq/seq+, the stages are sequential, but the content of a phase is essentially (with exceptions, later) executed in parallel.

Y86 Execution of Instructions

here are the various stages of instruction processing , everybody can sweep through , look at the results of my analysis. , It's easy to understand the picture. .

See the above instructions to deal with the various stages is not a hype AH. In fact, it is not complicated, because the use of a unified framework. The following points are summed up:

(1). The first thing to see is what the command is going to do, what its operand is, and the direction of the data flow.

For example, OPL, RRMOVL, IRMOVL, cmovxx all do not involve memory, is the execute phase of the execution of the results of the Vale to a program register. (Data Flow direction: Vale-> program Register).

For example, MRMOVL, the data flow direction of the POPL is: memory-and program register. Think it's going to take valm out of the memory and give this program register.

For example, the data flow direction of the RMMOVL is: program register, Memory, will definitely write to the memory.

(2). There are two sources of data written to the program register, one is Vale (OPL,RRMOVL, IRMOVL, PUSHL, POPL, call, RET,CMOVXX) and one is Valm (MRMOVL, popl).

(3). PUSHL, POPL, call, ret all involve the "stack" (memory), will update the%ESP (%esp+/-4: In the execution phase to calculate the Vale). Write the Vale back to%esp.

(4). OPL in the execution phase will be set CC, CMOVXX, jxx in the execution phase will have a judgment logic.

(5). Only RMMOVL, PUSHL and call need to write back to memory.

(6). Unified processing principle: In the excute phase, Vala as far as possible not to participate in the operation, the use of VALB to participate in the operation, in the memory phase, are Vala participate in the operation (in order to make PUSHL and RMMOVL Unified processing).

(7).

Doubt

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1. RRMOVL's execute phase does not require an operation, why do you want to execute "ValE = 0+vala"?

A: Using a unified framework, each instruction must pass through each stage. This also has the benefit of reducing the number of signal transfers. Write back is through the Vale and Valm, without needing vala.

2. Why is MRMOVL D (RB), RA instead of MRMOVL D (RA), RB?

A: Unified processing Mrmvol and RMMOVL. This ensures that the "execute phase, Vala try not to participate in the operation, using VALB participate in the operation."

3. The write back stage of the POPL RA requires two registers to be written. These two should be in order.

A: Yes. In order to ensure that the semantics of "POPL%ESP" are consistent with IA32, "R[%esp]<-vale" must precede "r[ra]<-valm", which means that 2 cycles is required to execute according to the rules that can only be update on the rising Edge ( violate the principle).

4. PUSHL Ra, why is there no problem?

A: Due to the SEQ CPU. Because the read value exists on a signal line (referred to as a vala signal). Even if the "Pushl%esp", the value of%ESP is already on the Vala signal line, just write the value of Vala back to the memory.

Reference article:

1.8280141

Computer operating System (II)---processor Architecture (iii) (RPM)