Computer Parallel Interfaces

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• Computer Parallel Interface (2)
• Computer Parallel interfaces (Abstract)

IEEE1284Signal and collation

The IEEE-1284 defines a one-to-one asynchronous bidirectional parallel interface. PC using a type connector, socket DB-25 pass, including 17 signal lines and 8 line, signal lines are divided into 3 groups, control line 4, status line 5, data line 8.

The printer uses a type-B connector, which is a 085inch pitch Champ connector of 36PIN, called the Centronics connector.

Description of each pin signal of 36PIN Centronics Connector

Type C: The new Mini-Centronics 36PIN connector, with a 050inch pitch, can be used for both the host and peripherals

Comparison of D-type 25-pin and 36-pin Centronics pins:

Pin definitions for type A, type B, and type C connectors:

4.IEEE1284Interface connection:

The signal correspondence between PC DB-25 and printer Centronics 36PIN connector:

Connection between PC side A (DB-25) and printer side B (Centronics 36PIN) connector:

Connection between PC side A (DB-25) and printer side C (Mini-Centronics 36PIN) connector:

Connection between the Mini-Centronics 36PIN and the Centronics 36PIN:

5.IEEE1284Hardware interface

IEEE-1284 defines two levels of interface compatibility, Level I is used for products that do not require high-speed mode, but require reverse channel capabilities; Level II is used for long cables and high-speed transfer rates.

The parallel interface outputs the logical level of the TTL standard, and the input signal must also comply with the TTL standard. This feature makes the interface Easy to apply in electronic design. Most PC parallel interfaces can absorb and output about 12mA of the current. If the application time is smaller than or greater than this value, the buffer circuit should be used.

To maintain compatibility with earlier Centronics interfaces, use an OC (open collector) drive with a pull-up resistor Standard Resistance Value of 2.2k or 4.7k. The control line and the status line only require the uplink resistance Rp. The data line and the Strobe line also require the series resistance Rs to match the line impedance, adjust the serial resistance value so that the sum of the output impedance with the drive is equal to the line impedance from 45 euro to 55 Euro. For example, if the output impedance of the driving IC is 15 euro, 33 euro series resistance is required.

IEEE-1284 interface chip:

Because the minimum output driving voltage is 2.4 V, the standard TTL + 5 V or low voltage TTL + 3.3V chip can be used.

Fairchild, ST, and ti all have similar chips, such as 74ACT1284, 74LVC161284, 74LV161284, and 74F1071.

6.IEEE1284Signal spec sheet

Thanks for the following information:

Materials of Wen zhengwei's original bulletin board

Http://www.interfacebus.com/Design_Connector_1284.html

Http://ckp.made-it.com/ieee1284.html

Http://www.fapo.com/1284int.htm

Http://zone.ni.com/devzone/cda/tut/p/id/3466

Http://www.homestead.co.uk/

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Posted on 1:45:50

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Computer Parallel Interface (2)

2.IEEE1284Defined5Working modes

To improve the performance of the Centronics interface and to be compatible with the previous standards, IEEE1284 defines five working modes:

SPP mode: Standard Parallel Port Standard Parallel interface, also known as Compatibility mode compatible mode, Nibble mode: from PC to peripherals 8-bit data lines, reverse 4-bit data lines

Byte mode: 8-bit bidirectional transmission with a speed of 50 kb/s to kb/s

EPP mode: Enhanced Parallel Port Enhanced Parallel interface, allowing high-speed byte transmission in any direction

ECP mode: Extended Capabilities Port Extended Parallel Interface, allowing PC to send data blocks

In compliance with IEEE 1284 standard, the Device ID (Device identification sequence) is used for Plug-and-Play configuration, making the parallel port easier to use. The same connector and cable connection mode can be used in various modes. Due to different hardware and programming methods, the transmission speed can range from 50 K Bits/s to 2 MB/s.

2.1)SPPMode:That is, the traditional Centronics parallel interface, also known as Centronics mode

Provides basic signals, including 8-bit data lines and four control lines (Strobe, Initialize Printer, Select Printer, and Auto Feed line) and five status lines (Busy, Acknowledge, Select, Paper Empty, Fault), need three different registers for data read and write operations.

The SPP mode is the most basic working mode. asynchronous and byte one-way transmission has a data rate between 50KB/s and 150KB/s. The AB-cable can be used for 6 meters, while the new CC-cable can be used for up to 10 meters.

Time series of the basic SPP Mode

When the printer is ready to receive data, set BUSY to low, and the host sends valid data to the data line, wait for at least ns and then send a STROBE negative pulse lasting at least NS, valid data must maintain at least 500 ns after the rising edge of STROBE. The printer receives data and sets BUSY to be valid to indicate data processing. When the printer completes data receiving, it sends an ACK pulse at least ns, and then clears BUSY to indicate that it is ready to receive the next byte of data.

The standard handshake signals of Centronics are slightly different. nStrobe is a negative pulse with a minimum width greater than 1 us, And nAck is a response negative pulse with a width greater than 5 us. Because the negative pulse of the nAck signal is short, generally, it is not queried, but Busy.

The host software transmits 1 byte of data through the parallel port in four steps:

1. Write valid data into the data register

2. Check the BUSY status line and wait for it to be invalid (0)

3. Write control registers to make STROBE valid (0)

4. Write control register to invalidate STROBE (1)

The minimum setup time, retention time, and pulse width required by the SPP mode limit its performance. Considering the software wait time, the maximum data transmission rate of IEEE1284 is 150 kbytes/s, the typical Centronics is 10 kbytes/s, which is sufficient for dot matrix row printers, but insufficient for high-speed laser printers.

Signal definition in SPP mode:

For parallel port operations, SPP defines registers and maps them to the I/O space of the PC. Registers include three consecutive registers with the parallel address as the base address. The parallel address is usually 3BCH, 278 H, and H, and both include data, status, and control registers, data, status, and control signal line operations are usually called data ports, status ports, and control ports. The address of printer Card 1 is usually 378 H, of which the data port is 0378 H, the status port is 0379 H, and the control port is 037AH. The address of printer Card 2 is usually 278 H, among them, the data port is 0278 H, the status port is 0279 H, and the control port is 027AH. Supports the new IEEE 1284 standard parallel port, uses 8 to 16 registers, the address is 378 H or 278 H, Plug-and-Play (Plug and Play) compatible port adapters can also be reloaded.

Definition of parallel registers:

Data Register: The address occupied is the base address of the parallel interface, which corresponds to 2-9 pins of the interface.

Status Register: the occupied address is the base address plus 1, which corresponds to 10, 11, 12, 13, and 15 pins of the interface. It is a read-only register, which contains an IRQ interrupt bit (formed by the opposite of Ack ), when an interruption occurs, the data bit is "0 ". Bit7 (pin 11) has the inverse feature when the input is + 5 V and the data value is "0.

Control Register: the occupied address is the base address plus 2, which corresponds to the interfaces, 16, and 17. Bit0, Bit1, and Bit3 have the inverse feature. Bit4 is an IRQ application. When "1" is written to Bit4, The ACK (PIN 10) signal is reversed to the IRQ signal of the interrupt request, usually IRQ5 or IRQ7.

The 3BCH, rjh, and 278H base addresses used for the parallel port almost all support the SPP, ECP, and EPP modes (the 3BCH address does not support the EPP and ECP modes on the early parallel port printer adapters ). The address segments of the three different base addresses are as follows:

Some integrated 1284 I/O controllers use FIFO buffer to transmit data known as Fast Centronics or Parallel Port FIFO Mode. They also use the SPP protocol, but use hardware to generate strobe signals to achieve control signal handshaking, this allows the data rate to exceed kb/s. However, this is not a standard model defined by IEEE 1284.

2.2)NibbleMode:A common method for obtaining reverse data from a printer or external device,

The Nibble mode uses four status lines to transmit data from peripherals to the computer. The standard parallel port provides five signal lines from peripherals to PCs to indicate the status of peripherals. Using these signal lines, Peripherals can send 1 byte (8-bit) data twice, each time a half-byte (nibble: 4-bit) is sent. Because nACK signals are generally used to provide peripheral interruptions, it is difficult to merge the transmitted nibble (half-byte) information into one byte through the Status register (Status register, the software must read status signals and perform corresponding operations to obtain the correct byte information. In Nibble mode, the data rate is 50 kbps (6 meters cable), and the data rate of the new 10 meters CC-cable is 150 kbps. The advantage of the Nibble mode is that all parallel PCs can execute this mode, but it can only be used for reverse channel low-speed scenarios.

The following table defines the signals of the Nibble mode:

Describes the basic sequence of Nibble mode.

Nibble mode data transmission steps:

1. When HostBusy is set to low, the host can receive data.

2. Peripherals output the first half-byte (nibble) to the status line.

3. Set PtrClk to low to indicate that nibble data is valid.

4. The host sets HostBusy as the high indicator to receive nibble data while processing

5. Set the PtrClk on the peripherals as the high-response host.

6. Repeat steps 1 to 5 to receive the second half byte (nibble)

The Nibble mode is similar to the SPP mode. The software needs to set and read the control signal lines of the parallel port to implement the Protocol. The Nibble mode and SPP mode are combined to establish a complete two-way channel, forming the simplest two-way transmission mode. From a PC to a peripheral 8-bit data line, the reverse 4-bit data line supports one-way printer interface, provides forward transmission at full speed and reverse transmission at half rate, the speed ranges from 50KB/s to 150KB/s.

2.3)ByteMode:Reverse transmission over data lines

Byte mode uses data lines to transmit 8-bit data from peripherals to the host. The 8-bit data cable of the standard parallel port can only be transmitted from the host to the peripherals in one way. The driver of the control data cable needs to be restrained so that the data can be transmitted from the printer to the computer. Data transmission in Byte mode, one Byte is transferred at a time, which is different from the two data cycles required in nibble mode. The speed is the same as that from the computer to the printer, between 50KB/s and 150KB/s, the new CC-cable can be used to reach 500 kbps over a 10-meter cable.

The following table defines the signal of the Byte mode:

Data transmission steps in Byte mode:

1. When HostBusy is set to low, the host can receive data.

2. Peripherals output the first byte data to the data line

3. Set PtrClk to low to indicate that byte data is valid.

4. The host sets HostBusy as high indicator to receive byte data while processing

5. Set the PtrClk on the peripherals as the high-response host.

6. Repeat steps 1 to 5 to receive other bytes of data.

Describes the basic sequence of the Byte mode.

The manufacturer first adds the 8-bit data line reading capability on the ibm ps/2 port to realize the Byte mode, making it a bidirectional port, called the Type 1 of the Extended Port. In addition, Type 2 and Type 3 are provided, using DMA. When Type 2 and 3 DMA write data, the DMA controller writes data to the data register, and the STROBE pulse is automatically generated. When the ACK is received from the peripherals, the DMA request is sent and the next byte is sent. You can set BUSY for peripherals to delay transmission. When Type 2 and 3 DMA read data, the ACK pulse generates a DMA request and initiates transmission to the system memory. The DMA controller reads the data register and the STROBE pulse is automatically generated. The DMA transmission of Type 2 and 3 follows the SPP mode sequence.

Although IBM has defined the Type 2 and 3 methods to improve the parallel port performance, only IBM computers implement this feature and lack software to support this DMA feature. In comparison, EPP and ECP are industrial standards supported by a wider range of hardware and software manufacturers.

2.4)EPPMode:Enhanced Parallel Port for high-speed bidirectional data transmission

Designed by Intel, Xircom, and Zenith Data Systems, EPP provides a high-performance parallel interface, which is part of the IEEE1284 standard and can be used in common with standard parallel interfaces, the Protocol has the same register ing relationship. The protocol is first implemented by the Intel platinum SL chipset (82360 I/O chip.

EPP mode signal Definition

The EPP mode has a data cycle and an address cycle. It provides four transmission cycle time series:

1. Data Writing Cycle Time Series

2. Data Reading cycle timing

3. Address write Cycle Time Series

4. Address reading Cycle Time Series

The data cycle sequence is used to transmit data between the host and peripherals. The address cycle sequence is used to allocate address, channel, command, and control information.

EPP address WRITE cycle: the host first sets WRITE *, sends the address signal to the data line, and sets ASTROBE *; the peripheral cancels WAIT * to indicate that the address byte is ready to be received; the host then cancels ASTROBE *; the peripheral stores the address data on the rising edge of ASTROBE *, and then sets WAIT * to indicate that you are preparing for the next cycle.

EPP address reading cycle: the host cancels WRITE * to keep the data line in high-impedance state. Set ASTROBE *. When the peripheral sends the address byte to the data line, cancel WAIT * to indicate that the address is valid. When the host detects that WAIT * is canceled, read the address, and then cancel the ASTROBE; then, place the data line in high-impedance state, set WAIT *, and instruct you to prepare for the next cycle.

EPP data WRITE cycle: the host sets WRITE *, sends data bytes to the data line, and sets DSTROBE *; the peripherals cancel WAIT * to indicate that the data is to be received; the host then cancels DSTROBE *; the peripheral stores data on the rising edge of DSTROBE *, and then sets WAIT * to indicate that the preparation starts the next cycle.

EPP Data Reading cycle: the host cancels WRITE * to keep the data line in high-impedance state. DSTROBE * is set. Peripherals send data bytes to the data line and cancel WAIT * to indicate that the data is valid; the host detects that WAIT * is canceled, reads data, and then cancels the DSTROBE *. The peripherals then place the data line in the high-impedance state, and sets WAIT * to indicate preparation for the next cycle.

EPP mode defines five registers outside the three SPP mode parallel registers, which are used to automatically send addresses or data to the parallel data line, and then automatically generate strobe) signal. The data, status, and control registers in EPP mode are configured in the same way as those in SPP mode.

Write the Data to the Auto Address Strobe register. The Data will be sent to the parallel Data line, and the ASTROBE * low pulse signal will be generated automatically; the Data will be written to any Auto Data Strobe register, the Data is sent to the parallel Data line along with the automatically generated DSTROBE * low pulse signal. When an Auto Data Strobe register is read, The DSTROBE * signal is controlled by the pulse and the level value is returned.

EPP register interface:

From the software perspective, the EPP mode extends the parallel port register of SPP. The SPP port includes three registers: Data, Status, and Control. The address is the offset of the base address ).

EPP registers are defined as follows:

By generating an I/O write command for "base_address + 4", the EPP controller generates the handshake signal and strobes for data transmission in the Data_Write cycle. The I/O commands for ports 0 to 2 will implement standard parallel port operations to ensure compatibility with standard parallel ports. For "base_address + 3" I/O operations, the address read/write cycle is generated. Ports 5 to 7 have different functions in different hardware. It can be used as a 16-bit or 32-bit software interface or as a configuration register, or it may not be used.

Seven software steps are required for data transmission at the standard parallel port. Other hardware and registers are added to EPP, And the handshaking signal for controlling strobes and data transmission is automatically generated through a single I/O command, ensure that the data is transmitted at the speed of the ISA bus. The maximum data rate is 2 Mbytes/s, which may reach 10 Mbytes/s on other platforms. The bus structure of EPP microprocessor makes it easy to communicate directly with peripheral hardware. The EPP mode also provides further block transmission capabilities. The use of the REP_IO command relies on the support of the host adapter.

Steps for Data Writing sequence in EPP mode:

1. The program executes the I/O write cycle for PORT4 (EPP Data Port)

2. The nWrite signal is valid and the data is sent to the parallel port.

3. Set datastrobe to be valid, and set nWAIT to low

4. Wait for the response from the peripherals (nWAIT becomes invalid)

5. The datastrobe setting is invalid and the EPP cycle ends.

6. ISA's I/O cycle ends

7. Set nWAIT to low, indicating the start of the next cycle

It is an instance of EPP Data Writing Time series, and the CPU signal nIOW is used to emphasize that all handshake is completed in one I/O.

Note that all data is transmitted in an isa I/O cycle. This indicates that the data transmission rate can be kb/s to 2 MB/s using the EPP Protocol, in this way, the performance of peripherals is close to that of the ISA card.

Because the interlock handshake signal protocol is used, data can be transmitted at a very low rate. The Nibble, Byte, EPP, and ECP modes all use the interlock handshake signal protocol. The so-called interlock handshake signal means that each change in the control signal requires a response from the other side.

The EPP mode allows High-Speed bytes transmission in any direction, but not at the same time. It is a half-duplex mode designed for Optical Drive, tape drive, hard drive, and network adapter. The data rate ranges from 500KB/S to 2 MB/S, the AB-cable can be used for 6 meters, while the new CC-cable can be used for up to 10 meters.

2.5)ECPMode:Extended Capability Port extends the function parallel interface, and can also achieve high-speed two-way Data Transmission

The ECP mode is proposed by Microsoft and Hewlett Packard and is an extension of the standard parallel port. It is used as an advanced communication mode for peripherals of printers and scanners, allows image data compression, FIFO (first-in-first-out) in the queue, and high-speed bidirectional communication. The data transmission speed is about 2-4 MB/S.

The ECP protocol redefined the SPP signal, as shown in the following table:

The ECP mode provides two data transmission cycle time series, which can be used in two directions:

1. data cycle

2. command cycle

There are two types of command cycles: RLE (Run-Length Count) and Channel address ).

RLE achieves real-time data compression with a compression ratio of up to 64: 1. It is especially used when printers and scanners transmit a large amount of raster image data (including a large number of identical data strings, however, it must be supported by both the host and peripherals. The channel address is different from the EPP address. It is used when a physical device includes multiple logical devices, such as FAX/Printer/Modem.

The ECP mode defines the forward transmission as the host to the peripheral, there are two kinds of forward transmission cycle, when the HostAck is high, indicates the data cycle; when the HostAck is low, the command cycle is carried out, data description uses RLE count or Channel address. Bit 8 in the Data byte is used to indicate RLE or Channel address. If bit 8 is 0, bit 1-7 describes Run Length Count (0-127 ), if bit 8 is 1, bit 1-7 describes the Channel address (0-127) and the time sequence of a data period and a command period.

The forward Transmission sequence of the ECP mode:

1. The host sends data to the data line and sets HostAck as high to indicate the start of a data cycle.

2. Set the HostClk to low to indicate that the data is valid.

3. Set PeriphAck to a high-response host.

4. The host is set to a high HostClk, which is an edge trigger signal used to store data to peripherals.

5. Set the PeriphAck to low to indicate that the device is ready to receive the next byte.

6. The loop is repeated, but this time it is command cycle, because HostAck is low

Note: Both interfaces use FIFO, And the sent data is considered to have been received. In step 2, The HostClk becomes high, data is triggered to enter the peripherals, and the data Pointer counter is updated. In some cases, this may cause data loss during transmission.

The ECP mode defines that reverse transmission is used to transmit data from peripherals to the host. During reverse transmission, when data on the parallel port is valid, the peripheral setting of PeriphClk is low, and the host setting of HostAck is low after receiving data. Describes the time sequence of the reverse channel command cycle following the data cycle:

It also shows that the ECP and EPP protocols are different. In EPP mode, the software can perform mixed read/write operations without additional protocols. in ECP mode, negotiation is required to change the data transmission direction. The host requires that the reverse transmission channel set nReverseRequest and wait for the response of the nAckReverse of the peripheral before performing reverse data transmission. In addition, if DMA transmission was previously performed, the software must wait for the DMA to complete or interrupt the DMA (to determine the exact amount of transferred data in FIFO) and then require the reverse channel.

Reverse Data and Command cycles in ECP Mode

1. When nReverseRequest is set to low on the host, the reverse transmission channel is required.

2. Set nAckReverse to low and respond to the host.

3. the peripherals send data to the data line and set PeriphAck to indicate a high data loop.

4. Set the PeriphClk of the peripherals to be valid for low indication data.

5. Host HostAck is set to high-validation

6. The PeriphClk is set to a high level for peripherals. This is an edge trigger signal used to store data to the host.

7. The host sets the HostAck to low, indicating that it is ready to receive the next byte.

8. The loop is repeated, but this is the command cycle because PeriphAck is low.

The use of ecp fifo weakens the association with ISA regardless of the DMA or programmable I/O mode. The software does not know the data transmission status accurately and only cares about whether the transmission is complete.

In Microsoft's specification book "The IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard", a general register and adapter working mode based on The isa ecp mode is defined. The ECP register utilizes six defined registers and only requires three I/O Ports. Note that the Register definition is related to the working mode.

ECP register description:

In ECP mode, six registers are defined out of three SPP mode parallel registers, which are used to automatically send addresses or data to the parallel data line, and then automatically generate strobe) signal.

The Address and Data FIFO of ECP include at least 16 bytes, which can be used for forward and backward transmission, smooth Data flow and improve Data rate. Write Data to the Address FIFO register, which is automatically sent to the parallel port. The Data FIFO register of ECP is used for Data transmission between the host and peripherals.

ECP mode parallel register configuration diagram:

The ECP mode is designed to achieve parallel plug-and-play performance and high-performance bidirectional transmission in Windows. The ECP mode allows High-Speed byte transmission in any direction and is also a half-duplex mode. Designed for printers and scanners, the data rate ranges from kb/S to 1 MB/S, and 6 meters can be transferred using the AB-cable, the new CC-cable can be used up to 10 meters. ECP mainly uses DMA instead of direct I/O operations to transmit large data blocks.

2.6) Work mode selection process (Negotiation):

A device may be designed to work in multiple modes, but cannot be used at the same time. You can only select one mode at a time. IEEE 1284 invented the negotiation mode. The host must determine the connectivity and usage mode of the connected peripherals and determine which IEEE1284 mode to use. This negotiation mode will not affect the devices in the past, an old-style Device does not respond to the negotiation time series, but devices that comply with the IEEE 1284 standard will respond to this time sequence, so that the host obtains the Device ID code ), select a high working mode through the ECR register operation.

The host uses the Device ID sequence to identify the parallel Device. Device ID is an ASCII string that defines the peripheral features and performance. Because there is no authorization center to assign device and manufacturer codes, in the Plug-and-Play system, the host must be able to determine and identify the added devices, and automatically install the required device driver.

All IEEE 1284 devices are in SPP mode when power-on. The process of selecting the IEEE 1284 working mode on the host is as follows:

1. Send the extensibility code of IEEE 1284 to the data line

2. Set the SelectIn signal line to high, and set AUTOFD to low

3. the peripherals are set to high PError, ACK, FAULT, and Select as IEEE1284 standard devices (if the peripherals do not set these signals, the host considers that the peripherals are not IEEE1284 devices ), then, perform the following operations.

4. Make STROBE low

5. Make STROBE high and AUTOFD low

6. If the extensibility code matches the provided mode, the peripherals set PError to low, FAULT to low, and Select to high.

7. Enable high ACK for peripherals, indicating that the status line is available

IEEE1284 extended code: Extensibility Request Bytes

The ECR register is used to set the current working mode, and is also used to determine the performance of the parallel port installed on the PC.

ECR register mode:

If you want to exit Nibble, Byte, or ECP mode, set SelectIn to low, and if you exit EPP mode, the host needs to set the INIT signal to be valid, and the peripherals will return to SPP mode.

If a parallel port supports both the SPP mode and other bidirectional modes, the first three registers are exactly the same as those of the standard parallel port to be compatible with the previous standard.

2.7) In different modes25PIN D-subDifferent definitions of connector signals:

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Posted on 1:43:28

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Computer Parallel interfaces (Abstract)

Personal computer (PC) accounts for the vast majority of the computer market, and the computers that most people can access and recognize are basically ibm pc computers and compatible computers, this computer uses an INTEL X86 hardware platform and a microsoft windows Operating System (early as a MS-DOS operating system) software platform with a variety of external devices and input and output interfaces, becoming a de facto industrial standard. Parallel interfaces are common I/O interfaces.

Parallel interfaces are generally called Centronics interfaces, also known as IEEE1284. They were first developed by Centronics Data Computer Corporation in the middle of 1960s. Centronics was originally designed as a parallel interface for dot matrix row printers. It was adopted by IBM in 1981 and later became a standard configuration for ibm pc computers. It uses the TTL level that has become the mainstream at the time. Each one-way parallel transmission of 1 byte (8-bit) data, the speed is higher than the current serial interface (only 1 bit can be transmitted at a time ), it is widely used and becomes the interface standard for printers. In 1991, Lexmark, IBM, Texas instruments, and other companies competed with other interfaces to expand their application scope. they improved the Centronics interface to enable high-speed bidirectional communication, in order to be able to connect the hosts machine, tape drive, optical drive machine, network equipment and other computer external equipment (peripherals), finally formed the IEEE1284-1994 standard, it is called "Standard Signaling Method for a Bi-directional Parallel Peripheral Interface for Personal Computers". The data rate increases from 10 kb/s to 2 Mbit/s ). However, in fact, this two-way parallel communication is not widely used, and parallel interfaces are still mainly used for printers and mappers. In other aspects, only a small number of devices are used, this interface is generally called the print interface or LPT interface (currently new printers tend to use USB or RJ-45 ETHERNET interfaces ).

1.IEEE1284Interface connector and Cable

Our common parallel port is usually the 25-pin D interface on the host, and the 36-pin spring interface on the printer (Centronics interface ).

The IEEE1284 Standard specifies three types of connectors, namely A, B, and C:

Type A: 25PIN DB-25 connector for host only.

DB-25 pass socket (also known as FEMALE or mother), used on PC, shape

25 pin D-SUB female connector at the PC

Corresponding pin-Shaped Cable plug (also known as MALE or MALE) and serial number

This type of DB-25 needle socket (also known as MALE or public), because the size is small, there are a few small printers (such as pos printer) Use (non-standard use ), but the cable should be short:

Type B: 36PIN 085inch pitch Champ connector, with a snap device, also known as Centronics connector, used only for peripherals

36PIN Centronics SOCKET (SOCKET or FEMALE), used on the printer, shape

36 pin CENTRONICS female connector at the printer

Corresponding 36PIN Centronics cable PLUG (PLUG) and serial number

Type C: The new Mini-Centronics 36PIN connector, also known as half-pitch Centronics 36 connector (HPCN36), also known as MDR36, 36PIN 050inch pitch, with a clamping device, it can be used on both hosts and peripherals. Currently, it is not common enough. As competitive new interface standards keep emerging, it is hard to see

Mini-Centronics 36PIN socket and serial number

36 pin MDR36 male connector

The new interface also adds two signal lines Peripheral Logic High and Host Logic High to detect whether the other end is powered on through the cable

The earliest Centronics parallel cable has a length of 2 meters and can only transmit data rates of 10 kb/s. It does not have high performance requirements. To increase the data rate to more than 2 Mb/s, many special requirements for the IEEE1284 cable are put forward:

1. Because it is parallel data, in order to avoid crosstalk between BIT data during transmission, each data line must be combined with a ground line to form a twisted pair structure.

2. The unbalanced Characteristic Impedance Between each pair of signal and the return ground wire is 62 euro +/-6 euro (in band 4m-16 MHz)

3. the crosstalk between wires cannot exceed 10%

4. The cable has a shielding layer and is connected to the shielding shell of the connector. It is enclosed with a 360-degree package.

The following six typical IEEE1284 cables are available: 10, 20, and 30 feet (about 3, 7, and 10 meters ):

AMAM: Type A Male to Type A Male (usually used for computer interconnection)

AMAF: Type A Male to Type A Female (generally used for extended cables or A-port parallel printers)

AB: Type A Male to Type B Plug (generally used to connect A computer with A common B-port printer)

AC: Type A Male to Type C Plug

BC: Type B Plug to Type C Plug

CC: Type C Plug to Type C Plug

Among them, the first three are commonly used cables, and the last three are cables related to the newly added C-interface.

Note: The parallel port on the PC is different from the serial interface DB-25

RS-232 serial port on PC general use DB-9 needle socket (also known as MALE or public)

Some legacy PCs are also equipped with DB-25 needle socket (also known as MALE or public) for COM2 use

RS-232 socket (also known as FEMALE or mother)

Chain connection: According to the IEEE 1284 chain connection specifications, a port can connect up to eight devices, and each chain connection device has two parallel connectors and one main connector (host connector) and a pass through connector ). The host connects to the master connector of the first device. Its direct connector connects to the master connector of the next device and connects them in sequence. Devices that do not support chained connections can be connected to the pass-through connector of the last device. However, currently, one-to-one connections are common, and this type of device is rarely seen.

Subminiature D connectors of various sizes (also known as D-Sub connectors ):

Various shell sizes: DA, DB, DC, DD, And DE.

Contact Count: 9, 15, 25, 37, and 50

Contact Count HD: 15, 26, 44, 62, 78 and 104

Power Supply: 3W3, 3WK3, 5W5, 8W8, and 3, 5, 8 single-row high-capacity power contacts

Type: Board Mount (Right Angle, Through-Hole, Surface Mount, Dual Port, Press-fit, Wire Wrap), Cable (IDC, Crimp Snap-in, Solder Cup)

D-Sub connector terminology:

HD: High Density, 3 rows of feet in 2 rows of shell, such as 15PIN in 9PIN Shell

Filtered: EMI or RF interference suppression

Common D-Sub connectors on PCs:

9-pin de d-Sub connector: Used as RS-232 serial port

15-pin da d-Sub connector: Used as a VGA video output port

25-pin db d-Sub connector: Used as the parallel port/printer port

(DB9, DB15, and DB25)