Computer Systems: Article 6 chapter (memory hierarchy)

Reference: In-depth understanding of computer systems, sixth chapter

6.1.1 Random access memory ram

1. Static RAM (SRAM) vs. dynamic RAM (DRAM)

First of all. Basic concepts: SRAM stores a bit structure to six transistors, and the DRAM stores a bit structure as a capacitor (dram can reach a higher density than SRAM). So SRAM is more expensive than DRAM, and the effect is faster access. (a desktop system SRAM no more than a few megabytes, DRAM can have hundreds of to thousands of megabytes)

And then. The concept of an advanced point. SRAM has a steady state. DRAM (capacitance) has a lot of situations that make the DRAM need to refresh each bit by "reading again, writing again" Every time it takes a cycle.

(Some DRAM uses error-correcting codes such as 38bit to encode 32 bits to solve the problem)

At last.

SRAM is used as a fast cache. Can be on-chip, can also be off-chip (able to sit on a chip with the CPU, can also be separated from chip), DRAM is used to make the main memory and graphics system frame buffer (is expected to be "video card").

2. What is the image of the traditional dram?

A W DRAM unit (a unit that stores a bit) forms a supercell (assuming that the DRAM chip is a matrix, then a supercell is a matrix element)---"

The D-Supercell form a matrix of a*b. Form a DRAM chip so that the chip has a a*b*w bit (the reason why D Supercell make up a matrix instead of a linear array is to reduce the number of address pins on the chip.

However, the disadvantage of matrix organization is to send the address in 2 steps: Row + column. This adds an interview time)---"

Multiple DRAM chips are packaged in a memory module. This memory module is on the expansion slot of the hatchet motherboard. ---》

The chip flows into and out of the chip via a foreign connector called a PIN

3. How to access main memory

First of all. Understand who is in the computer to access the main memory? is the CPU.

and main memory exists outside the CPU (off the chip)

Then, a general overview of the flow of main memory: the flow of data flows through the shared electronic circuitry of the bus to and fro between the CPU and the DRAM.

Specifically, say.

1) different computer systems for the bus has a different design, this book is used is one of the advanced bus architecture, the detailed structure is shown in Figure 6-6. So, here's how the CPU of the main memory interview is based on this bus architecture.

2) The data flows through the bus (which has the system bus and memory bus) between the chips (CPU--I/O bridge--main memory).

4. Basic concepts of speed at all levels in the memory hierarchy

The top tier refers to the CPU registers (which, as the name implies, should be on chip). Access speed is a clock cycle;

Next is the smaller (several megabytes) SRAM-based fast cache memory, which can be visited at several X-four clock cycles (ns level);

Then there is the larger (hundreds of trillion-gigabit) DRAM-based main memory, which can be visited in 10~10^2 clock cycles.

Next comes the very large local disk, which is 10^3 times as much as 2,500 times times the time it takes to DRAM. MS level);

Finally, there is a layer on the remote server disk. Need to access them through the network.

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Computer Systems: Article 6 chapter (memory hierarchy)