Design of asynchronous serial port based on FPGA with fault-tolerant energy management

First, the problem stems from a project. Originally is a very simple multi-port transceiver FIFO Access data of the small program, through the computer verification is also available, and the next machine board communication between the loss of a number of problems.

The reasons for this analysis are as follows:

My serial module is based on the privileges of the Student's Development Board program modification, that is, once the signal line is pulled down, it is believed that the data began to transmit, then the number of the number, then a few 10 bit (1 start bit + 8 bits of data +1 stop bit), even after a byte, go back to detect the signal line is pulled low This program cannot be detected when the wrong code is issued at the end of the issue. To be able to identify the wrong code, both the start and stop bits must be detected to determine whether the byte is complete.

After a weekend of writing, the new module was released. The module entrance has a RS232_RX signal, the exit has rx_data[7:0] and a flag signal line, flag is a byte full end of the sign.

The main idea of the new module is to add the steps of judging the frame end based on the original module. The approach is:

1, ready to do a 10-way redundancy, each road to detect RS232_RX falling edge. (It should be less than that) 10-way redundancy is a priority, when the first detection of the falling edge, the first start count, start the 10 bit data acquisition. When the first count starts, the second count is started when the falling edge is encountered, and so on. That is, after the first boot count of the receiving module, each time a falling edge is encountered, the count is started.

2, when the first number to the 10th bit, that is, the stop bit, if the acquisition of 1, then also proves that the collection is the stop bit, then all the redundant count after the stop. If the first stop bit is not collected to 1, it proves that the transmission error, the first path does not receive a complete frame of data, then output data, waiting for the second stop bit acquisition results. And so, knowing that the stop bit of a data is 1, the remaining redundant path is set to output data.

3, this 10-way redundancy is just a frame of data service, that is, 1 bytes, to ensure that a single byte can be collected correctly.

After the above modification, the program can collect the data correctly. But the above modification is not perfect, the reason is that the acquisition of bit is in the center of the baud rate acquisition, if a frame rate of 1bit time is 100ms, then I in the first time to collect data, record. This does not guarantee that the data is correct, there may be errors before the acquisition, or just after the acquisition of the error. If this is the case and there is a high data in the position where the stop bit is supposed to be, then it is wrong to assume that the frame data is correct.

So the most secure approach is that each bit of data acquisition three times, about 1/6 3/6 5/6, the three locations collected, if all the same, only to judge this bit to collect the correct. This will greatly improve the accuracy of data acquisition.

After the change of the module has the advantage that each time a complete byte is received, there will be a high signal generation (FLAG), for real-time requirements of a strong task, helpful. Every data received can be judged and manipulated immediately without having to open up a large buffer class register.

Design of asynchronous serial port based on FPGA with fault-tolerant energy management