Embedded Linux bare Metal Development (13)--I2C Communication

Embedded Linux Bare Metal Development (13)--i²c communication a ,IIC Protocol 1. Introduction ofIIC bus

    i2c (Inter integrated circuit) bus is a The company developed a two-wire serial bus for connecting microcontrollers and peripherals. i2c Bus is a serial data bus, only two signal lines, one is two-way cable sda scl i2c A data byte transmitted on the bus is made up of eight bits. The bus has no limit on the number of bytes per transfer, but each byte must be followed by an answer bit.

The IIC bus is a serial bus that is used to connect a microcontroller and its peripherals, with the following characteristics:

A, Two bus lines: one serial data line (SDA), one serial clock line (SCL)

B, each device connected to the bus have a the only address (only within the board)

C, a simple master-slave relationship between devices that transmit data

D, hosts can be used as host transmitters or host receivers

E, Multi-Host bus, when two or more hosts initiate data transfer simultaneously, the data can be corrupted by conflict detection and quorum

F, Serial 8-bit bidirectional data transfer, bit rate up to 100kbit/s in standard mode, up to 400kbit/s in fast mode, up to 3.4mbit/s in high-speed mode

G, The filter on chip can increase the interference function and ensure the complete data

H, The number of ICS connected to the same bus is limited by the maximum capacitance of the bus

2.IIC bus structure

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Transmitters: devices that send data to the bus

Receiver: A device that receives data from the bus

Host: Device that initiates/stops data transmission and provides a clock signal

Slave: The device addressed by the host machine

Multi-Host: can have multiple hosts trying to control the bus, but will not destroy the data

Quorum: When multiple hosts attempt to control the bus, quorum allows only one host to gain control of the bus and the information it transmits is not compromised

Synchronization: The process of synchronizing clock signals with multiple devices

The I²c bus uses a pull-up resistor to connect the positive supply. When the bus is idle, the two lines are high. The low level of the output of any device connected to the bus will lower the signal of the bus, that is, the SDA and SCL of each device are both line "and" relationship.

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Each device connected to the I²C bus has a unique address. The data transfer between the host and other devices can be sent from the host to other devices, the host is the transmitter. The device receiving data from the bus is the receiver.

In a multi-host system, there may be several hosts attempting to initiate the bus to transmit data. To avoid confusion, the I²c bus will be arbitrated by bus to determine which host controls the bus.

The validity of data bits is defined as:

During data transfer of the I²C bus, the data on the data line must remain stable during the high-level clock signal, and only the high or low status on the data line is allowed to change when the signal on the clock line is low.

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Second, Communication Timing

The communication sequence is the level change of the communication line in chronological order.

1. IIC bus signal type

The IIC bus has 3 types of signals in the process of transmitting data: Start signal, end signal and response signal

A, start Signal (S): When the SCL is high, the SDA jumps from high to low to indicate the start signal and start transmitting the data

B, End Signal (P): When the SCL is high, the SDA jumps from low to high, indicating the end signal and ending the transmit data

C, response Signal (ACK): After receiving 8 bits of data, the receiver pulls down the SDA level in the 9th clock cycle. That is, when the IC receiving the data receives 8bit data, it emits a specific low-level pulse to the IC that sent the data, indicating that the data has been received. After the CPU sends a signal to the controlled unit, waits for the controlled unit to send a response signal, the CPU receives the response signal, according to the actual situation to make the judgment whether to continue to transmit the signal. If the response signal is not received, the fault is determined as the controlled unit.

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Start signal s and end signal p

Both the start and stop signals are sent by the host, and the bus is in the occupied state after the start signal is generated, and the bus is idle after the termination signal is generated.

Devices connected to the I²C bus can easily detect start and stop signals if they have a hardware interface to the I²C bus. For some MCU that does not have an I²C bus hardware interface, in order to detect the starting and terminating signals, the data line SDA must be sampled two times within each clock cycle.

Once the receiving device receives a complete data byte, it may be necessary to do some other work, such as handling internal interrupt service, etc., may not immediately receive the next byte, the receiving device can pull the SCL line low level, so that the host is waiting. Until the receiving device is ready to receive the next byte, release the SCL line so that it is high so that data transfer can continue.

2. IIC Bus data transmission format

Each byte sent to the SDA line must be 8 bits, and the number of bytes that can be sent per transmission is unrestricted. Each byte must be guaranteed to be 8 bits in length. When data is transmitted, the highest bit (MSB) is transmitted, and each transmitted byte must be followed by an answer bit (i.e., a total of 9 bits in a frame).

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If you do not continue to receive or send after some other functions from the machine, the slave can pull down the SCL to force the host into a wait state. When the slave is ready to receive and release the SCL, the data continues to be transferred. If the host also needs to complete some additional functions during data transfer, the leaf can pull down the SCL to occupy the bus.

When a transmission is initiated, the host emits an S-signal and then emits 8 bits of data. The first 7 bits are the slave address, the 8th bit represents the transmission direction (0 for the write operation, and 1 for the read operation). The selected slave sends a response signal. Then transmit a series of bytes and response bits. Finally, the host sends the P signal to the end.

For some reason the slave does not answer the host address signal (such as the slave is doing real-time processing to receive the data on the bus), it must put the data line high, and the host produces a termination signal to end the bus data transfer.

If a slave responds to the host but cannot continue to receive more data after a period of data transfer, the slave can notify the host by a "non-reply" to the first data byte that cannot be received, and the host should issue a termination signal to end the continuation of the data transmission.

When the host receives the data, it receives the last data byte and must send a signal to the slave to end the transmission. This signal is implemented by a "non-response" to the slave. The SDA line is then released from the machine to allow the host to produce a termination signal.

There are no ACK signals in the following three cases:

A, when the slave is unable to respond to the slave address (from the machine busy other things cannot respond to the IIC bus operation or the address is not on the machine), the SDA line is not pulled low in the 9th SCL period, i.e. there is no ACK signal. At this point, the host sends a P signal to terminate the transmission or resend an S signal to start a new transmission

B, The slave receiver does not emit an ACK signal when it cannot receive more data during transmission. The host realizes this, sending a P signal to terminate the transmission, or start a new transmission by sending an S signal from the newly

C, The host receiver does not emit an ACK signal when it receives the last byte, so the SDA line is released from the machine transmitter, allowing the host to send a P signal to end the transmission

Data frame format

The data signals transmitted on the I²C bus are generalized, including both the address signal and the real data signal.

after the starting signal must be transmitted a slave address (7 bits), the 8th bit is the data transfer direction bit (r/), with "0" for the host to send data (T), "1" indicates that the host receives data (R). Each data transfer is always terminated by the end signal generated by the host.  However, if the host wants to continue to occupy the bus for new data transfer, it can not produce a stop signal, immediately again send the start signal to another slave to seek .

In the process of data transfer in the bus, there are several combinations of the following methods:

A, The host sends data to the slave, and the data is transferred in the same direction throughout the transfer process:

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Note: A shaded section indicates that the data is transferred from the host to the slave, and no shaded portions indicate that the data is transmitted from the slave to the host.

a means answer, A represents a non-reply (High level). s represents the start signal and P indicates the terminating signal.

B, The host reads the data from the machine immediately after the first byte

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C, During transmission, when the direction of transmission needs to be changed, both the start signal and the slave address are repeatedly generated once, but the two read/write direction bits are reversed exactly.

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Second, IIC Controller

IIC Controller:

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Clock Source: Pclk_psys

Bus Control logic unit: generation of IIC Communication timing (Setup I2ccon , I2cstat )

Shift Register: the data 1bit shift to SDA line

Comparator + address Register: Compares the address to the address register address as it will be received when used from the device.

I2ccon : Clock Configuration

I2cstat : operation mode and condition bit send

I2CADD:IIC Address

I2cds: Data Shifter

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Embedded Linux bare Metal Development (13)--I2C Communication