Embedded Linux bare Metal Development (eight)--s5pv210 interrupt processing process

Embedded Linux Bare Metal Development (eight)--s5pv210 Interrupt processing process

an interrupt is a process that the CPU inserts into another program during the execution of the current program due to hardware or software reasons. The interruption process due to hardware causes is unpredictable, that is, random, and soft interrupts are pre-arranged. The signal source that caused the interruption is called the interrupt source. interrupts are divided into external interrupts and internal interrupts based on the source of the interrupt source. interrupts originating from inside the SOC (internal peripherals) are called internal interrupts. The interrupt source is from outside the SOC, and interrupts generated by interrupting the corresponding GPIO pin are called external interrupts. There are four states of interruption:

Inactive (does not activate):no active or suspended interrupts
Pending (hang):This interrupt can be either hardware-aware or software-generated and is waiting for the processor to process.
Active (Active):The interrupt is recognized by the processor from the interrupt source in the universal Interrupt controller and is processing the interrupt, and no processing is complete.
Active and pending (active and pending):The processor is processing an interrupt, and the universal Interrupt Controller has a pending interrupt.

First, s5pv210 Interrupt system

The s5pv210 has a total of 4 vector interrupt controllers, supporting 93 interrupt sources.

Main vector Interrupt control register:

vic0intenable : Interrupt Enable

Vic0intenclear : Interrupt Disable

Vic0intselect : Interrupt Selection, Irq/fiq

Vic0irqstatus : IRQ Interrupt Status Register

Vic0fiqstatus : Fiq Interrupt Status Register

vic0vectaddr : The ISR address that corresponds to the interrupt source

vic0address : Vector address Register, When an interrupt occurs, the hardware will interrupt the current interrupt Service Routines ISR Address automatic copying from register vicvectaddr to register vicddr

S5pv210 turns off Fiq and IRQ in the BL0 phase, so you need to open the IRQ manually when the program starts.

Open Interrupt

mov r0, #0x13

MSR cpsr_cxsf, R0

Second, Interrupt Processing Process

S5PV210 Interrupt Processing process:

1, the preparation before the interruption of processing

A, initialize the interrupt controller

The initialization of an external interrupt controller includes: The peripheral Gpio pin is set to the external interrupt mode, the initialization of the external interrupt control register, and the interrupt vector control register initialization.

Initialization of interrupt controllers for internal interrupts includes: initialization of interrupt vector control registers

B. Vicnvectaddr of the ISR to the vector interrupt controller that binds the interrupt source

C, enable interrupt source interrupt

2. Interrupt Processing Process

A, the anomaly vector table jumps to the IRQ entry

The CPU receives an interrupt notification when processing a regular task, so s5pv210 jumps to the IRQ exception vector address of the Iram exception vector table According to the Irom Cure code. The starting address of the assembly code snippet that is responsible for protecting the site, processing interrupts, and recovering the site is assigned to the IRQ exception vector address as the entry for processing interrupts.

B, protect the site of interruption

Before processing interrupts to protect the scene, the main work is: Set the IRQ mode stack, the R0-R12,LR pressure stack save (because of the pipeline, LR is generally the current execution of the instruction address plus 8,LR minus 4 is the next command to run the address).

C. Execute Interrupt Handler

Check to see if the VICNADDR register has an ISR function address, and if so, execute the ISR. The ISR is usually bound to vicnvectaddr before the interrupt occurs.

D. Recovery site

After the ISR is executed, the R0-R12,LR in the stack are r0-r12,pc separately, and the program will automatically jump to the regular task execution based on the value of the PC.

The general model for interrupt handling is as follows:

#define IRQ_STACK (0XD0037F80)

. Global Irq_exception

Irq_exception:

set the stack in IRQ mode

LDR Sp,=irq_stack

protect the scene

Save LR

Sub LR,LR, #4

Save r0~r12

STMFD SP!,{R0-R12,LR}

BL Irq_handler // interrupt handlers

Recovery Site

LDMFD sp!,{r0-r12,pc}^

third, interrupt handler and interrupt service routine ISR

Interrupt handlers and interrupt service routines ISR are two very confusing concepts, but the two are two different concepts. The interrupt handlers in the kernel are related to interrupt service routines such as:

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each interrupt source that triggers the interrupt corresponds to an interrupt handler, each of which corresponds to multiple interrupt service routines. after registering the Interrupt service routine , the Interrupt Service routine is suspended in the interrupt request queue . An interrupt handler is a handler for interrupt vectors, and if multiple devices share an interrupt source, the interrupt handler must invoke the Interrupt service routine ISR for each device.

In bare metal, because each interrupt source (terminal number) has only one corresponding interrupt vector address register vicvectaddr, there is only one interrupt service routine for each medium-fault handler.

Four, handling keystrokes with external interrupts

Programming model for Interrupt processing:

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1, check the schematic diagram, find the corresponding external interrupt source key GPIO

A, consult the Backplane circuit diagram key related parts:

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The Smart210 Development Board has a total of four user keys, the corresponding PIN is xeint16--xeint19

B, check the core board circuit schematic key related parts:

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The key pin xeint16--xeint19 corresponding GPIO pin is Gph2_0--gph2_3

#define GPH2CON (* (volatile unsigned long *) 0XE0200C40 )

setting the GPIO pin for the K1--K4 key to external interrupt mode

Gph2con |= 0xffff<<0;

2. Consult the documentation and set the external interrupt control register

The external interrupt of the s5pv210 is generated by the gpio corresponding to the external interrupt, and the external interrupt register is located in the Gpio section of the document.

Main registers for external interrupts:

Ext_int_ N _con : Set how external interrupts are triggered

Ext_int_ N _pend : Interrupt suspend Register, 32 bits, each corresponding to an external interrupt source,

Ext_int_ N _ Mask: Interrupt Mask Control Register

the external interrupt number for four user keys is Ext_int 16-- Ext_int 19, select the second set of external interrupt control registers.

Interrupt Trigger Mode

low-level triggering

Ext_int_2_con &= ~ (0xFFFF);

Falling Edge Trigger

Ext_int_2_con |= (0x2<<0 | 0x2<<4 | 0x2<<8 | 0x2<<12);

Double Edge Trigger

Ext_int_2_con |= (0x4<<0 | 0x4<<4 | 0x4<<8 | 0x4<<12);

Open External Interrupt

Ext_int_2_mask &= ~ (0xf<<0);

purge pending, need to write 1 when cleared

Ext_int_2_pend |= 0xf<<0;

3. set vector Interrupt control register

Disable all interrupts

Vic0intenclear = 0xFFFFFFFF;

Vic1intenclear = 0xFFFFFFFF;

Vic2intenclear = 0xFFFFFFFF;

Vic3intenclear = 0xFFFFFFFF;

Select the interrupt type as IRQ

Vic0intselect = 0x0;

Vic1intselect = 0x0;

Vic2intselect = 0x0;

Vic3intselect = 0x0;

Qing vicxaddr

VICXADDR: The address of the interrupt handler function for the interrupt currently being processed

vic0addr = 0;

vic1addr = 0;

vic2addr = 0;

vic3addr = 0;

After setting the Gpio external interrupt mode, external interrupt control register, and vector interrupt control register, the external interrupt can reach the internal CPU. For internal interrupts, there is no need to set up a GPIO, external interrupt controller, just set the vector interrupt control register, interrupt can reach the CPU.

4.CPU processing interrupt

When the CPU receives an interrupt notification, it can follow the interrupt processing process.

Project source code see attachment, the project compiles after Smart210 normal burn run.

Power on the serial port to print the numbers, press the K1-K4 key when printing information.

Reference blog:

Samsung s5pv210(arm-cortex A8) interrupt process plot (CSDN im Liu No Shi )

Interrupt Handlers & Interrupt Service Routines ( Chinaunix Helianthus_lu )

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Embedded Linux bare Metal Development (eight)--s5pv210 interrupt processing process