Embedded Linux applications: technical features of ARM architecture

Article title: Embedded Linux applications: technical features of the ARM architecture. Linux is a technology channel of the IT lab in China. Includes basic categories such as desktop applications, Linux system management, kernel research, embedded systems, and open source.

When developing and designing the first ARM chip, some machines at that time, such as Digital PDP-8, Cray-1, and IBM 801, proposed the concept, in addition, there are many characteristics in the future development of the server. However, the only example of the server, no lock pipeline processor), and they were only used for teaching and research. The ARM processor is the first one developed for commercial purposes. The architecture adopted by ARM has both inheritance and abandonment for the current Proteus architecture, that is, it has been carefully studied based on the actual design needs without mechanical copying. Arm's architecture uses several features designed by the Berkeley RISC processor, but also gives up some other features. These features include:

· Load/Store architecture

· Fixed 32-bit commands

· 3 address instruction format

Among the features adopted by the Berkeley whitelist design, arm designers discard the following technical features:

· Register window

In the early stage, due to the fact that the Berkeley prototype included the register window, the mechanism of the register window closely accompanied by the concept of the RISC, which became a major feature of the general RISC. The register window is used in the register heap of the Berkeley Proteus processor to make 32 registers visible at any time. Both the process entry and exit access a new set of registers, thus reducing data congestion and time overhead between the processor and memory caused by register storage and recovery. This is an advantage of having a register window. However, the existence of the register window increases the cost of the chip because a large number of registers occupy a large amount of chip resources. Therefore, the register window is not used when the ARM processor is designed. Although the shadow registers used to handle exceptions in arm are similar in concept to the window registers, when processing processes in exception mode, the number of shadow registers is very small.

· Delayed transfer

The transfer interrupts the smooth flow of the instruction assembly line, resulting in the "cut-off" problem of the assembly line. most of the RISC processors use delay transfer to improve this problem, that is, transfer is performed only after subsequent instructions are executed. Latency transfer is not used in the original arm because it makes the exception handling process more complex.

· All commands are executed in one cycle

Arm is designed to use the least clock period to access the memory, but not all commands are executed in a single cycle. For example, ARM7TDMI is widely used in low-cost ARM application fields. data and commands occupy the same bus. when the same storage is used, even the simplest Load and Store commands require at least two accesses to the memory (one command and one data read/write ). When the access to memory needs more than one cycle, it will be used more than one cycle. Therefore, not all ARM commands are executed within a single clock cycle. a few commands require multiple clock cycles. The high-performance arm9TDMI uses separate data and command registers to perform single-cycle operations on the command memory and data access memory of the Load and Store commands.

The initial ARM design was most concerned with the simplicity of the design. ARM's simplicity is more evident in ARM's hardware organization and implementation than in the instruction set structure. The combination of simple hardware and instruction sets is the ideological basis of the RISC System. However, ARM still retains some CISC features and thus achieves a higher code density than pure Proteus, this allows arm to gain the power efficiency and smaller core area advantages at the beginning.