Embedded Linux bare Metal Development (11)--nandflash

Embedded Linux Bare Metal Development (11)--nandflash First, about Nand Flash

    nand lash Yes flash, has the advantages of large capacity, fast rewriting speed, and is suitable for storing large amounts of data n and , send instructions The address and data are all via a 8/16-bit wide bus (I/O interface) to the internal register.

Nandflash is divided into SLC and MLC two categories. SLC is all called Single-level Cell, single-layer unit flash, MLC is all called multi-level Cell, multi-layer unit flash. SLC stores one bit of data per unit, and MLC uses a large number of voltage levels, each unit stores two bits of data, the data density is relatively large. SLCWaferthe production cost is higher, the efficiency is much better than the MLC. SLC wafer can be repeated write times of about 100,000 times, and MLC Wafer write times to at least 10,000 times to calculate the standard. MLC Disadvantages are:slower read and write speeds,MLC energy consumption is higher than SLC,MLC theory has a relatively low maximum number of writes,MLC Price is lower than SLC.

Second, nandflash Memory structure 1.nandflash memory structure

NAND flash memory consists of blocks, the basic unit of Block is page (page). Each block is comprised of 16, 32, or 64 page. Most NAND flash devices contain a 512-byte data area (datastore) and an extended 16-byte Spare area (alternate zone) within each page (page). The size of each page is 512+16=528 bytes , called small page.

capacity of large capacity (1Gbig or more) NAND flash,page larger , the size of the data area (Datastore region) within each page is 2048 bytes, and the Spare area (alternate region) size is 64 bytes.

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the read and burn of NAND Flash is based on the page, and nor Flash based on byte or word. The erase operation of NAND Flash is based on block. There are three basic operations on NAND Flash: Reading a page, burning a page, and erasing a block.

In a read operation on a page, 528 bytes of data within the page is first transferred to the data register and then output. In the burn of a page, 528 bytes of data within the page are first written into the data register and then stored in the storage array. In the erase operation of a block, a contiguous set of pages is erased under a separate operation.

2. Alternate Unit Structure

NAND Flash manufacturers use the Spare area (alternate zone) in the production process to identify bad blocks, and all the bytes in the Spare area (alternate zone) can be used by the user to store data just like the bytes in the data area.

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3. Bad block (Invalid block) Management

Since the NAND structure was designed to be used as a low-cost multimedia memory, the standard specification was to allow bad block to exist. As long as the bad block's capacity is less than 2% of the total capacity that is allowed. If there is a bad storage area in a block, it will be identified as the wrong block. The bad block list can be stored on a good block in a chip, or on another chip in the same system. The bad block list is required due to the limited number of read and erase times that NAND flash can perform. Since all flash memory will eventually be worn and can no longer be used, the bad block list needs to be used to keep track of the bad blocks found in use. Allowing the presence of bad blocks can help increase the output of the chip and reduce costs. Each block is independent and is isolated by bit lines, and the presence of bad blocks does not affect the normal operation of those other blocks.

Bad blocks are generally divided into two types: produced during production, and generated during use. When block is found to be bad block, it is usually identified by non-FF at the NO. 517 byte of the first two pages of the block. The bad block produced during use is not identified by the factory .

A, Skip block Method (skip bad block mode)

Read all the spare areas in the memory first. The addresses identified as bad block are collected. Next, the data is continuously written to the target flash device. When the destination address is identical to the previously collected bad block address, the block is skipped and the data is written to the next good block. Then continue to retain the identification information for the alternate zone in the bad block. So before the program import executes, the user's system can create a bad block address list by reading the information in the spare area (alternate zone).

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B, Reserved Block Area method (reserved block zone mode)

Bad block can be replaced by a good block (block) in the user's system.

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C, error Checking and Correction (bug detection and correction)
ECC error correction mechanism is used to make the stored data complete and correct

Third, Nandflash Interface

The Nandflash chip has a storage particle and internal management interface circuitry, and the external SOC accesses the Nandflash chip based on the Nandflash interface timing. The Nandflash controller is integrated inside the s5pv210.

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The Nandflash pin functions are as follows:

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Nandflash Command code:

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The Nandflash chip internal interface circuitry can receive commands sent by the external Soc, interacting with the Soc. The operation of the external Soc on the Nandflash chip must be carried out in accordance with the Nandflash specified timing.

Third, Nandflash Common operations 1. Bad block check

The nandflash needs to be uniformly erased (by block erase) before it is used, and the 1 is populated after erasing. Erase block, compares each byte in the block to 0xFF, if not 0xFF, is the bad block.

2. page Burn (page write operation)

The page needs to be erased before it is burned, and if the page is not erased before it is burned, the burned data will be wrong. When burning, the SOC sends the burning command, the burning address, the burning data and so on into the Nandflash through command line and IO line. The Nandflash chip interface circuitry receives the page data into the buffer and then concentrates the storage particles into the nandflash. The burning process takes some time, and the SOC's Nandflash controller waits for Nandflash to burn, and the Nandflash controller of the SOC will continue to read the page burning state during the wait. When the SOC's Nandflash controller receives the correct status response, it confirms that the page burning has succeeded, and if it has not received the correct state, it is considered that the block where the burn page resides is a bad block.

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The page burn programming process is as follows:

A. Send the chip selection signal

B. Send page Burn command first cycle command 0x80

C, random write the value of an address within a page

D, send page Write command 0x85

E, write in-page offset address

F. Write Data

G, send page Burn command second cycle command 0x10

H, wait status

I, read status, page burning successfully cancel the chip selection signal, failed to cancel the chip selection signal

3. Block Erase

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The erase operation must specify a block-aligned address. The block erase programming process is as follows:

A, get the address of the erase block (block alignment)

B. Send the chip selection signal

C, send the Erase command, the first cycle of the command 0x60, the second cycle of the address of the block, the third cycle of the command 0xd0.

D, clear status, wait status.

E, read status, Erase success cancel the chip selection, Erase failed to cancel the chip selection.

4. Page Read

Page Read Programming Flow:

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A. Send the chip selection signal

B, send the page Read command, the first cycle of the command 0x00, the second cycle to send the page address, the third cycle of sending commands 0x30

C, wait status

D, send the page to read the first cycle of the command 0x05

E, write in-page offset address

F, send page read second cycle command 0xe0

G, read data

H, check the status, if the read successfully, cancel the chip selection signal, read failed to cancel the chip selection signal.

Five,s5pv210 nandflash Controller

Key features of the Nandflash controller:

Support for 512B,2KB,4KB,8KB page Nandflash

Software mode: Direct access to Nandflash chip, support read/burn/erase Nandflash chip

Nandflash chip interface bus with 8bit support

Generation, detection, and indication of hardware ECC

Supports SLC/MLC type Nandflash chip

ECC with 1/4/8/12/16 bit support

SFR interface: Support Byte, half word, word access data and ECC data register, Word access other registers.

Soc via control SFR (Nandflash Controller)

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nfconf : Nandflash Configuration Register

Nfcont : Nandflash Control Register

NFCMMD : nandflash Command Register

nfaddr : Nandflash Address Register

Nfdata : Nandflash Data Registers

nfsblk : Burn block Start address

nfeblk : Burn block End Address

Nfstat : Status Register

Six, Nandflash Programming Practice

The Smart210 Nandflash is a 512MB SLC type.

Circuit schematic view

Refer to the core Board circuit schematic for the Nandflash section,

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Nandflash chip Select signal PIN is XM0CSN2 , in the core Board circuit schematic search XM0CSN2 Know that Nandflash connected to memory Port0, corresponding to Gpio mp01-mp03

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The GPIO configuration is as follows:

Mp0_1con = 0x22333322;

Mp0_2con = 0x00002222;

Mp0_3con = 0x22222222;

Project source code see attachment, after compiling in Smart210 Burn can run normally, can normal Nnandflash erase, burn, read and so on test operation.

Reference blog:

Nandflash Introduction ( CSDN drunk Caterpillar. )

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Embedded Linux bare Metal Development (11)--nandflash