Embedded Linux kernel i²c subsystem detailed

1.1 I²c Bus Knowledge

1.1.1 I²c Bus physical topological structure

The I²c bus is very simple in physical connection, consisting of SDA (serial data line) and SCL (serial clock line) and pull-up resistor respectively. The principle of communication is to generate the signals required by the I²c-Bus protocol to transmit the data by controlling the order of the SCL and SDA lines at high and low levels. In the bus idle state, these two lines are generally pulled up by the pull-up resistor above, maintaining a high level.

1.1.2 I²c Bus Features
Each device on an I²C bus can be used as a master or slave device, and each device corresponds to a unique address (which can be learned from the data sheet of the I²C device), which is used by the master and slave devices to determine which device to communicate with, in a typical application, We use the CPU with the I²c Bus interface module as the main device, the other devices attached to the bus as slave devices.
The number of devices that can be hooked up on an i²c bus is limited by the maximum capacitance of the bus 400pF, and is also limited by the device address bit if the same type of device is hooked up.
I²C bus data transmission rate in the standard mode up to 100kbit/s, fast mode up to 400kbit/s, high-speed mode up to 3.4mbit/s. Usually through the I²C bus interface programmable clock to achieve the transfer rate adjustment, but also with the resistance of the pull-up resistor connected.
The primary device on the I²C bus and the data transfer in bytes (8 bits) between the devices.

1.1.3 I²c Bus Protocol
The I²C protocol stipulates that the transmission of data on the bus must take a starting signal as a starting condition, with an end signal as the stopping condition of the transmission. The start and end signals are always generated by the main device. When the bus is idle, the SCL and SDA remain high, and when the SCL is high and the SDA jumps from high to low, a starting condition is generated, and when the SCL is high and SDA is low to high, a stop condition is generated. After the starting condition is generated, the bus is busy, the master-slave device of this data transmission is exclusive, the other I²C devices cannot access the bus, and after the stop condition is generated, the master-slave device of this data transmission will release the bus and the bus is idle again. ：

After understanding the starting and stopping conditions, let's take a look at how the data is transmitted in this process. As we mentioned earlier, the data transfer is in bytes. When the main device generates each clock pulse on the SCL line, a data bit is transmitted on the SDA line, and when a byte is transferred from high to low in the order of the data bits, then from the device will pull down the SDA line, back to the main device an answer bit, it is considered that a byte is actually transferred complete. Of course, not all byte transmissions must have an answer bit, for example: When the data sent from the main device is no longer received from the device, a negative answer bit is returned from the device. The process of data transfer:

In the previous we also mentioned that each device on the I²C bus corresponds to a unique address, the data transmission between the master and slave devices is based on the address, that is, the main device before transmitting valid data must first specify the address from the device, the address specified process and the process of data transmission above the same, But most of the device's address is 7 bits, and then the protocol specifies that the address is added a minimum bit to indicate the direction of the next data transmission, 0 indicates that the main device writes data from the device, and 1 indicates that the primary device reads data from the device. ：

1.1.4 I²c Bus operation
The operation of the I²c bus is actually the read and write operation between the master and slave devices. It can be broadly divided into the following three operating conditions:
First, the primary device writes data from the device. The data transfer format is as follows:

Second, the master device reads the data from the device. The data transfer format is as follows:

Third, the primary device writes data from the device, then restarts the starting condition, and then reads the data from the device, or the primary device reads the data from the device and then restarts the starting condition, followed by the main device writing data from the device. The data transfer format is as follows:

The third operation in a single master device system, the repetition of the start condition mechanism is more efficient than stopping the transmission after stop and then turning on the bus again.

1.2 i²c Bus Hardware interface Circuit example

1.2.1 I²c Bus Hardware interface Circuit example one

This circuit is designed based on the LPC2368 ARM7 chip, using its internal I²C interface as the main device, using ADT75 and sc16is740 as the two slave devices of the I²C bus application.

The ADT75 is a temperature sensor device with an I²c interface, and its address is described in the data sheet as follows:

Thus, the address of the A0, A1, A2 pin connection, we are here to the example is A0, A1, A2 all to the high level, so its address is: 1001111 (that is, 0x4f), but also by the Protocol to add a minimum bit (direction bit, default to write direction), So finally this temperature sensor as from the address of the device is: 10011110 (i.e. 0x9e).

The sc16is740 is an extended UART with an i²c or SPI interface (using the 8th foot to determine the use of the I²c or SPI interface, we require the I²c interface here, so the 8th foot is high). According to the data sheet, we can also know that the address is related to A0, A1, we here A0 high level, A1 low level. So the address of this device as slave device is: 10010010 (i.e. 0x92).

1.2.2 I²c Bus Hardware interface Circuit example two

This circuit is an application of the I²c bus interface on the Mini2440 Development Board. We can see that the SDA and the SCL line are connected with a 10K pull-up resistor. The AT24C08 is a 8Kbit EEPROM memory (note 8Kbit, or 1KB), according to the description of the device address section of the data sheet, the address of the AT24C08 is: 1010+a2a1a0+ direction bit, Where 1010 is the type identifier of the EEPROM, only using A2 to determine the bus access to the device's slave address, where the low level, so 0;a1 and A0 is the device internal page address, in the device erasure or programming, although the low level, but the device does not use the PIN input value , meaning that the value of A1 and A0 is set by the software.

1.3 Example of an I²C bus drive out of the operating system (example of a circuit sample)

1.3.1 LPC2368 in the I²c interface Register description
There are three i²c bus interfaces in the LPC2368, represented as I2C0, i2c1, and I2C2, each with 7 registers per I²c interface. Each of them is:
i²c Control Set Register (i2conset): 8-bit register, you different settings are different control of the I²c bus.

-bit	Symbol	Describe	Reset Value
1:0	-	Reserved, the user software does not write to it 1. The value read from the reserved bit is not defined	NA
2	Aa	Declares an answer flag. 1 o'clock will generate an answer for situations that need to be answered	0
3	SI	I²C Interrupt flag. The position bit when the i²c state is changed	0
4	Sto	Bus stop condition control. 1 issue a stop condition when the bus detects a stop condition, the STO automatically zeroing	0
5	Sta	Bus start condition control. 1 Enter main mode and issue a starting condition	0
6	I2en	Bus enable control. 1 in order to enable	0
7	-	Reserved, the user software does not write to it 1. The value read from the reserved bit is not defined	NA

I²c Control Clear 0 Register (I2CONCLR): 8-bit register, the corresponding in the I2conset register is zeroed.

-bit	Symbol	Describe	Reset Value
1:0	-	Reserved, the user software does not write to it 1. The value read from the reserved bit is not defined	NA
2	Aac	Declares the answer flag to clear 0 bits. Writes to this bit the AA bit in the 1-clear 0 i2conset Register	0
3	Sic	Interrupt flag cleared 0 bits. Writes the SI bit in the 1-clear 0 I2conset register to the bit	0
4	-	Reserved, the user software does not write to it 1. The value read from the reserved bit is not defined	NA
5	STAC	Starting condition clear 0 bits. Writes to this bit the STA bit in the 1-clear 0 i2conset Register	0
6	I2enc	The bus is forbidden to control. Write the I2en bit in the 1-clear 0 i2conset Register	0
7	-	Reserved, the user software does not write to it 1. The value read from the reserved bit is not defined	NA

i²c Status Register (i2stat): 8-bit read-only register for monitoring the real-time status of the bus (there may be 26 states).

-bit	Symbol	Describe	Reset Value
2:0	-		0
7:3	Status	These bits give the real-time status of the I²c interface, the different values represent different states, and the status code please refer to the data sheet	0x1F

i²c Data Register (I2DAT): 8-bit register, the data in the I2dat remains stable during SI placement.

-bit	Symbol	Describe	Reset Value
7:0	Data		0

i²c Slave address Register (I2ADR): 8-bit register, I²c bus is used when slave mode. This register is not valid in main mode.

-bit	Symbol	Describe	Reset Value
0	Gc		0
7:1	Address	The I²C device address from the mode	0x00

Sch Duty Cycle Register (I2SCLH): 16-bit register, which defines the number of PCLK periods that are maintained for the SCL high level.

-bit	Symbol	Describe	Reset Value
15:0	Sclh	SCL High Cycle selection count	0x0004

SCL Duty cycle Register (I2SCLL): 16-bit register that defines the number of PCLK periods that are maintained for the SCL low level.

-bit	Symbol	Describe	Reset Value
15:0	Scll	SCL Low Cycle selection count	0x0004

As we mentioned in the preceding I²c bus feature, the rate of the I²c bus is adjusted by a programmable clock, that is, the I2SCLH and I2SCLL registers must be set by the software to select the appropriate data frequency and duty ratio. The frequency is derived from the following formula (FPCLK is the frequency of PCLK).

1.3.2 LPC2368 in the I²c bus operation
We've talked about the operation of the I²c bus in 1.1.4, but that's just a description of the protocol and timing, so how do we get it out of the software? Let's talk about the problem next.
There are two ways to read and write a master-slave device on an i²c bus, one is to use polling, and the other is to use the interrupt mode. The polling method is to determine the current state value of the I²c status register in a loop, and then proceed to the next step based on the state of the bus. The interrupt mode is to enable I²C interrupt, register the I²C Interrupt service program, read the current status value of the I²c status register in the service program, and then determine the next operation according to the status value.
Regardless of which method is used, it appears that the value of the I²c status register is critical. What do these status values mean? Below we describe some commonly used status values (refer to the data sheet for detailed status value meanings).

0X08: Indicates that the main device has issued a starting condition to the bus;
0X10: Indicates that the main device has issued a duplicate starting condition to the bus;
0x18: Indicates that the primary device has sent one from the device address (write direction) to the bus and received an answer from the device;
0x20: Indicates that the primary device has sent one from the device address (write direction) to the bus and receives a non-response from the device;
0X28: Indicates that the primary device has sent a data byte to the bus and received a response from the device;
0X30: Indicates that the primary device has sent a data byte to the bus and received a non-response from the device;
0x40: Indicates that the primary device has sent one from the device address (read direction) to the bus and received an answer from the device;
0X48: Indicates that the primary device has sent one from the device address (read direction) to the bus and received a non-response from the device;
0X50: Indicates that the primary device has received a data byte from the bus and returned a reply;
0X58: Indicates that the primary device has received a data byte from the bus and returned a non-reply;

1.3.3 Sample Code
First, the polling method reads and writes the bus:

Refer to the data sheet of the device for the operation of the device's internal registers. For example, to read the temperature value of the thermal sensor only needs to call: I2c0_readregister (Channel_temperature, Adt75a_temp, &value), if the read is successful, The data in value is the temperature data in the temperature sensor is read via the I²c bus.

Second, interrupt mode read and write bus:
Here from the device address definition, the I²C control register macro definition and the I²c initialization is similar to the above poll, just to add the interrupt request code in the initialization function, the interrupt service program name is: I2c0_exception. The above code is no longer posted here, only the key code is posted here.

Embedded Linux kernel i²c subsystem detailed