embeded Linux switch--88e6321/88e6320

Switch Register:

With the MDIO_CPU and MDC_CPU access registers, the PHY device supports IEEE Serial Management Interface (SMI) or remotely managed Ethernet frames.

The device supports 2 types of SMI address usage models.

1. Use one of the 32 possible device addresses. (Multi-piece mode)

2. Use all 32 possible device addresses. (single-chip mode)

The device address and mode used for the addr[4:0] configuration pin after reset.

Multi-chip Address mode:

When using the multi-slice address mode of the SMI interface, the device responds with 32 possible SMI device addresses of 1, and can share the SMI interface with multiple devices. The SMI address used is determined by the addr[4:0] configuration foot.

In this mode, only the registers of the two devices are directly accessible, the SMI Command register and the SMI data register.

Both registers are used to indirectly access all other device registers (and any register that may be attached to it)

Indirect access to other device registers is achieved by setting the DEVADDR and regaddr bits of the SMI Command register to point to device register access.

Use the DEVADDR and REGADDR values defined for the device in single-chip addressing mode.

Multi-chip addressing mode is enabled when the addr 4:0 configuration pin has a non 0 value on the rising edge of the RESETN.

The ADDR 4:0 configuration pin also defines a single SMI address that the device will respond to.

To avoid collisions, this requires that all devices on the same SMI interface use a unique addr 4:0 value.

In this mode, the SMI address of 0x00 is not supported because the addr 4:0 pin places these devices in a single-chip addressing mode.

Not to be continued ....

　　

　　

embeded Linux switch--88e6321/88e6320